2.2.5. Registers

ARM processors have 37 registers. The registers are arranged in partially overlapping banks. There is a different register bank for each processor mode. The banked registers give rapid context switching for dealing with processor exceptions and privileged operations. See ARM Architecture Reference Manual for a detailed description of how registers are banked.

The following registers are available:

Thirty general-purpose, 32-bit registers

Fifteen general-purpose registers are visible at any one time, depending on the current processor mode, as r0, r1, ... , r13, r14.

By convention, r13 is used as a stack pointer (sp) in ARM assembly language. The C and C++ compilers always use r13 as the stack pointer.

In User mode, r14 is used as a link register (lr) to store the return address when a subroutine call is made. It can also be used as a general-purpose register if the return address is stored on the stack.

In the exception handling modes, r14 holds the return address for the exception, or a subroutine return address if subroutine calls are executed within an exception. r14 can be used as a general-purpose register if the return address is stored on the stack.

The Program Counter (PC)

The Program Counter is accessed as r15 (or pc). It is incremented by one word (four bytes) for each instruction in ARM state, or by two bytes in Thumb state. Branch instructions load the destination address into pc. You can also load the PC directly using data operation instructions. For example, to return from a subroutine, you can copy the link register into the PC using:

    MOV  pc,lr

During execution, r15 (pc) does not contain the address of the currently executing instruction. The address of the currently executing instruction is typically pc–8 for ARM, or pc–4 for Thumb.

The Current Program Status Register (CPSR)

The CPSR holds:

  • copies of the Arithmetic Logic Unit (ALU) status flags

  • the current processor mode

  • interrupt disable flags.

The ALU status flags in the CPSR are used to determine whether conditional instructions are executed or not. See Conditional execution for more information.

On Thumb-capable or Jazelle®-capable processors, the CPSR also holds the current processor state (ARM, Thumb, or Jazelle).

On ARMv5TE, and ARMv6 and above, the CPSR also holds the Q flag (see The ALU status flags).

On ARMv6 and above, the CPSR also holds the GE flags (see Parallel add and subtract) and the Endianness bit (see SETEND).

On ARMv6T2 and above, Thumb-2 introduces new state bits to the CPSR. These are used by the IT instruction to control conditional execution of the IT block (see IT).

Saved Program Status Registers (SPSRs)

The SPSRs are used to store the CPSR when an exception is taken. One SPSR is accessible in each of the exception-handling modes. User mode and System mode do not have an SPSR because they are not exception handling modes. See the chapter describing Handling Processor Exceptions in RealView Compilation Tools v2.2 Developer Guide for more information.

Copyright © 2002-2005 ARM Limited. All rights reserved.ARM DUI 0204F
Non-Confidential