4.2.7. PLD

Preload. The processor can signal the memory system that a load from an address is likely in the near future.

The address can be an immediate offset from the PC, or an immediate offset, register offset, or shifted register offset, from any register.

Implementation of PLD is optional. If it is not implemented, it executes as a NOP.

Syntax

There are three forms of the PLD instruction:

  • immediate or zero offset

  • register offset or shifted register offset

  • PC-relative.

The syntax of the three forms is as follows, in the same order:

PLD{cond} [Rn {, #offset}]
PLD{cond} [Rn, +/-Rm {, shift}]
PLD{cond} label

where:

cond

is an optional condition code (see Conditional execution).

Note

This is an unconditional instruction in ARM. cond is only allowed in Thumb-2 code, using a preceding IT instruction.

Rn

is the register on which the memory address is based.

offset

is an immediate offset. If offset is omitted, the instruction is a zero offset instruction.

Rm

is a register containing a value to be used as the offset. Rm must not be r15.

shift

is an optional shift.

label

is a program-relative expression. See Register-relative and program-relative expressions for more information.

Immediate offset

The offset is applied to the value in Rn before the preload takes place. The result is used as the memory address for the preload. The range of offsets allowed is:

  • –4095 to +4095 for ARM instructions

  • –255 to +4095 for Thumb-2 instructions.

Zero offset

The value in Rn is used as the address for the preload.

Register or shifted register offset

In ARM, the value in Rm is added to or subtracted from the value in Rn. In Thumb-2, the value in Rm can only be added to the value in Rn. The result used as the memory address for the preload.

The range of shifts allowed is:

  • LSL 0 to 3 for Thumb-2 instructions

  • Any one of the following for ARM instructions:

    • LSL 0 to 31

    • LSR 1 to 32

    • ASR 1 to 32

    • ROR 1 to 31

    • RRX

PC-relative

The assembler calculates the offset from the PC for you. The assembler generates an error if label is out of range.

Address alignment for preloads

No alignment checking is performed for preload instructions.

Architectures

This ARM instruction is available in ARMv5TE and above.

This 32-bit Thumb-2 instruction is available in all T2 variants of the ARM architecture.

There is no 16-bit Thumb PLD instruction.

Copyright © 2002-2005 ARM Limited. All rights reserved.ARM DUI 0204F
Non-Confidential