### 4.4.3. SMUL`xy` and SMLA`xy`

Signed Multiply and Multiply Accumulate, with 16-bit operands and a 32-bit result and accumulator.

#### Syntax

````SMUL`<`x`><`y`>{`cond`} `Rd`, `Rm`, `Rs`
```
````SMLA`<`x`><`y`>{`cond`} `Rd`, `Rm`, `Rs`, `Rn`
```

where:

`<x>`

is either `B` or `T`. `B` means use the bottom half (bits [15:0]) of `Rm`, `T` means use the top half (bits [31:16]) of `Rm`.

`<y>`

is either `B` or `T`. `B` means use the bottom half (bits [15:0]) of `Rs`, `T` means use the top half (bits [31:16]) of `Rs`.

`cond`

is an optional condition code (see Conditional execution).

`Rd`

is the destination register.

`Rm, Rs`

are the registers holding the values to be multiplied.

`Rn`

is the register holding the value to be added.

#### Usage

Do not use r15 for `Rd`, `Rm`, `Rs`, or `Rn`.

`SMULxy` multiplies the 16-bit signed integers from the selected halves of `Rm` and `Rs`, and places the 32-bit result in `Rd`.

`SMLAxy` multiplies the 16-bit signed integers from the selected halves of `Rm` and `Rs`, adds the 32-bit result to the 32-bit value in `Rn`, and places the result in `Rd`.

#### Condition flags

These instructions do not affect the N, Z, C, or V flags.

If overflow occurs in the accumulation, `SMLAxy` sets the Q flag. To read the state of the Q flag, use an `MRS` instruction (see MRS).

### Note

`SMLAxy` never clears the Q flag. To clear the Q flag, use an `MSR` instruction (see MSR).

#### Architectures

These ARM instructions are available in ARMv6 and above, and E variants of ARMv5.

These 32-bit Thumb-2 instructions are available in T2 variants of ARMv6 and above.

There are no 16-bit Thumb versions of these instructions.

#### Examples

```    SMULTBEQ    r8, r7, r9
SMLABBNE    r0, r2, r1, r10
SMLABT      r0, r0, r3, r5
```

#### Incorrect examples

```    SMLATB      r0,r7,r8,r15    ; use of r15 not permitted
SMLATTS     r0,r6,r2        ; use of S suffix not permitted
```
 Copyright © 2002-2005 ARM Limited. All rights reserved. ARM DUI 0204F Non-Confidential PDF version