4.2.12. LDREX and STREX

Load and Store Register EXclusive.

Syntax

LDREX{size}{cond} Rd, {Rd2,} [Rn {, #offset}]
STREX{size}{cond} Rd, Rm, {Rm2,} [Rn {, #offset}]

where:

size

is the size of the data to be loaded or stored. size must be one of:

B

unsigned Byte

H

unsigned Halfword

-

omitted for Word

D

Doubleword.

cond

is an optional condition code (see Conditional execution).

Rd

is the destination register. After the instruction, this contains:

  • for LDREX, the data loaded from memory

  • for STREX, either:

    0

    if the instruction succeeds

    1

    if the instruction is locked out.

Rd2

is the second destination register for doubleword loads.

Rn

is the register holding the memory address.

Rm

is the source register holding the data to store to memory.

Rm2

is the second source register for doubleword stores.

offset

is an offset applied to the value in Rn. offset is only allowed in Thumb-2 instructions, and only if size is omitted. The value of offset can be any multiple of four value in the range 0 to 1020. If offset is omitted, an offset of 0 is assumed.

LDREX

LDREX loads data from memory.

  • If the physical address has the Shared TLB attribute, LDREX tags the physical address as exclusive access for the current processor, and clears any exclusive access tag for this processor for any other physical address.

  • Otherwise, it tags the fact that the executing processor has an outstanding tagged physical address.

STREX

STREX performs a conditional store to memory. The conditions are as follows:

  • If the physical address does not have the Shared TLB attribute, and the executing processor has an outstanding tagged physical address, the store takes place and the tag is cleared.

  • If the physical address does not have the Shared TLB attribute, and the executing processor does not have an outstanding tagged physical address, the store does not take place.

  • If the physical address has the Shared TLB attribute, and the physical address is tagged as exclusive access for the executing processor, the store takes place and the tag is cleared.

  • If the physical address has the Shared TLB attribute, and the physical address is not tagged as exclusive access for the executing processor, the store does not take place.

Restrictions

r15 must not be used for any of Rd, Rn, Rm, Rd2, or Rm2.

Rd must not be the same register as any of Rm, or Rm2. For STREX, it must not be the same register as Rn.

Rd and Rd2 must not be the same register.

In the ARM LDREXD instruction, Rd must be an even numbered register, and not r14.

In the ARM STREXD instruction, Rm must be an even numbered register, and not r14.

Usage

Use LDREX and STREX to implement interprocess communication in multiple-processor and shared-memory systems.

For reasons of performance, keep the number of instructions between corresponding LDREX and STREX instruction to a minimum.

Note

The address used in a STREX instruction must be the same as the address in the most recently executed LDREX instruction. The result of executing a STREX instruction to a different address is unpredictable, that is, it cannot be relied upon.

Differences between the ARM and Thumb-2 instructions

In Thumb-2, the word LDREX and STREX instructions have an optional offset from the base register. None of the ARM load and store exclusive instructions can have offsets.

In Thumb-2, the doubleword LDREXD and STREXD instructions can use any two general-purpose registers for the data. The ARM instructions are restricted to using consecutive registers.

Exceptions

Data Abort.

Architectures

These ARM instructions, without size, are available in ARMv6 and above.

These ARM instructions, with size, are available in ARMv6T2 and above.

These 32-bit Thumb-2 instructions are available in T2 variants of ARMv6 and above.

Examples

    MOV r1, #0x1                ; load the ‘lock taken’ value
try
    LDREX r0, [LockAddr]        ; load the lock value
    CMP r0, #0                  ; is the lock free?
    STREXEQ r0, r1, [LockAddr]  ; try and claim the lock
    CMPEQ r0, #0                ; did this succeed?
    BNE try                     ; no – try again
    ....                        ; yes – we have the lock
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