4.2.8. LDM and STM

Load and Store Multiple registers. Any combination of registers r0 to r15 can be transferred in ARM state, but there are some restrictions in Thumb state.

See also PUSH and POP.

Syntax

op{addr_mode}{cond} Rn{!}, reglist{^}

where:

op

can be either:

LDM

Load Multiple registers

STM

Store Multiple registers.

addr_mode

is any one of the following:

IA

Increment address After each transfer. This is the default, and can be omitted.

IB

Increment address Before each transfer (ARM only).

DA

Decrement address After each transfer (ARM only).

DB

Decrement address Before each transfer.

cond

is an optional condition code (see Conditional execution).

Rn

is the base register, the ARM register holding the initial address for the transfer. Rn must not be r15.

!

is an optional suffix. If ! is present, the final address is written back into Rn.

reglist

is a list of one or more registers to be loaded or stored, enclosed in braces. It can contain register ranges. It must be comma separated if it contains more than one register or register range (see Examples).

See Restrictions on reglist in 32-bit Thumb-2 instructions.

^

is an optional suffix, available in ARM state only. You must not use it in User mode or System mode. It has the following purposes:

  • If the instruction is LDM (or LDMIA) and reglist contains the PC (r15), in addition to the normal multiple register transfer, the SPSR is copied into the CPSR. This is for returning from exception handlers. Use this only from exception modes.

  • Otherwise, data is transferred into or out of the User mode registers instead of the current mode registers.

Restrictions on reglist in 32-bit Thumb-2 instructions

In 32-bit Thumb-2 instructions:

  • the SP cannot be in the list

  • the PC cannot be in the list in an STM instruction

  • the PC and LR cannot both be in the list in an LDM instruction.

16-bit instructions

16-bit versions of a subset of these instructions are available in Thumb-2 code, and in Thumb code on other Thumb-capable processors.

The following restrictions apply to the 16-bit instructions:

  • all registers in reglist must be Lo registers

  • Rn must be a Lo register

  • addr_mode must be omitted (or IA), meaning increment address after each transfer

  • writeback must be specified.

In addition, the PUSH and POP instructions can be expressed in this form. Some forms of PUSH and POP are also 16-bit instructions. See PUSH and POP for details.

Loading to r15

A load to r15 (pc) causes a branch to the instruction at the address loaded.

Loading or storing the base register, with writeback

If Rn is in reglist, and writeback is specified with the ! suffix:

  • if the instruction is STM or STMIA and Rn is the lowest-numbered register in reglist, the initial value of Rn is stored

  • otherwise, the loaded or stored value of Rn is unpredictable, that is, it cannot be relied upon.

Architectures

These ARM instructions are available in all versions of the ARM architecture.

These 32-bit Thumb-2 instructions are available in T2 variants of ARMv6 and above.

These 16-bit Thumb instructions are available in all T variants of the ARM architecture.

In T variants of ARMv5 and above, a load to r15 also causes:

  • in ARM state, a change to Thumb state, if bit[0] of the value loaded is 1

  • in Thumb state, a change to ARM state, if bit[0] of the value loaded is 0.

The state change behavior can be disabled by setting the L4 bit (bit[15]) in cp15. See ARM Architecture Reference Manual for more details.

Examples

    LDM     r8,{r0,r2,r9}      ; LDMIA is a synonym for LDM
    STMDB   r1!,{r3-r6,r11,r12}

Incorrect examples

    STM     r5!,{r5,r4,r9} ; value stored for r5 unpredictable 
    LDMDA   r2, {}         ; must be at least one register in list
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