4.3.8. MOV and MVN

Move and Move Not.


MOV{S}{cond} Rd, Operand2
MVN{S}{cond} Rd, Operand2



is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation (see Conditional execution).


is an optional condition code (see Conditional execution).


is the destination register.


is a flexible second operand. See Flexible second operand for details of the options. See also Wide constants.


The MOV instruction copies the value of Operand2 into Rd.

The MVN instruction takes the value of Operand2, performs a bitwise logical NOT operation on the value, and places the result into Rd.

In certain circumstances, the assembler can substitute MVN for MOV, or MOV for MVN. Be aware of this when reading disassembly listings. See Instruction substitution for details.

Wide constants

In MOV instructions, Operand2 can take any value in the range 0-65535, in addition to the normal range of Operand2 values. These wide constants cannot be used with MVN instructions.

You cannot use the S suffix with a wide constant.

You cannot use r15 as Rd with a wide constant.

Use of r15

You cannot use r15 for Rd, or in Operand2, in the Thumb-2 MOV or MVN instructions. The remainder of this section applies to the ARM instructions.

If you use r15 as Rd, the value used is the address of the instruction plus 8.

If you use r15 as Rd:

  • Execution branches to the address corresponding to the result.

  • If you use the S suffix, the SPSR of the current mode is copied to the CPSR. You can use this to return from exceptions (see the Handling Processor Exceptions chapter in RealView Compilation Tools v2.2 Developer Guide).


Do not use the S suffix when using r15 as Rd in User mode or System mode. The effect of such an instruction is unpredictable, that is, it cannot be relied upon, but the assembler cannot warn you at assembly time.

You cannot use r15 for Rd or any operand in any data processing instruction that has a register-controlled shift (see Flexible second operand).

Condition flags

If S is specified, these instructions:

  • update the N and Z flags according to the result

  • can update the C flag during the calculation of Operand2 (see Flexible second operand)

  • do not affect the V flag.

16-bit instructions

The following forms of these instructions are available in Thumb code, and are 16-bit instructions when used in Thumb-2 code:

MOVS Rd, imm

Rd must be a Lo register. imm range 0-255.


Rd and Rm must both be Lo registers.

MOV Rd, Rm

In ARMv5 and earlier, either Rd or Rm, or both, must be a Hi register. In ARMv6 and above, this restriction does not apply.


These ARM instructions are available in all versions of the ARM architecture.

These 32-bit Thumb-2 instructions are available in T2 variants of ARMv6 and above.

These 16-bit Thumb instructions are available in all T variants of the ARM architecture.


    MVNNE   r11, #0xF000000B ; ARM only. This constant is not available in T2.

Incorrect example

    MVN     r15,r3,ASR r0   ; r15 not permitted with register controlled shift
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