4.3.10. TST and TEQ

Test bits and Test Equivalence.

Syntax

TST{cond} Rn, Operand2
TEQ{cond} Rn, Operand2

where:

cond

is an optional condition code (see Conditional execution).

Rn

is the ARM register holding the first operand.

Operand2

is a flexible second operand. See Flexible second operand for details of the options.

Usage

These instructions test the value in a register against Operand2. They update the condition flags on the result, but do not place the result in any register.

The TST instruction performs a bitwise AND operation on the value in Rn and the value of Operand2. This is the same as an ANDS instruction, except that the result is discarded.

The TEQ instruction performs a bitwise Exclusive OR operation on the value in Rn and the value of Operand2. This is the same as a EORS instruction, except that the result is discarded.

Use the TEQ instruction to test if two values are equal, without affecting the V or C flags (as CMP does).

TEQ is also useful for testing the sign of a value. After the comparison, the N flag is the logical Exclusive OR of the sign bits of the two operands.

Use of r15

You cannot use r15 for Rn, or in Operand2, in the Thumb-2 TST or TEQ instructions. The remainder of this section applies to the ARM instructions.

If you use r15 as Rn, the value used is the address of the instruction plus 8.

You cannot use r15 for any operand in any data processing instruction that has a register-controlled shift (see Flexible second operand).

Condition flags

These instructions:

  • update the N and Z flags according to the result

  • can update the C flag during the calculation of Operand2 (see Flexible second operand)

  • do not affect the V flag.

16-bit instructions

The following form of the TST instruction is available in Thumb code, and is a 16-bit instruction when used in Thumb-2 code:

TST Rn, Rm

Rn and Rm must both be Lo registers.

Architectures

These ARM instructions are available in all versions of the ARM architecture.

These 32-bit Thumb-2 instructions are available in T2 variants of ARMv6 and above.

The 16-bit Thumb TST instruction is available in all T variants of the ARM architecture.

Examples

    TST     r0, #0x3F8
    TEQEQ   r10, r9
    TSTNE   r1, r5, ASR r1

Incorrect example

    TEQ     r15, r1, ROR r0     ; r15 not permitted with register
                                ; controlled shift
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