4.3.2. ADD, SUB, RSB, ADC, SBC, and RSC

Add, Subtract, and Reverse Subtract, each with or without Carry.

See also Parallel add and subtract.

Syntax

op{S}{cond} Rd, Rn, Operand2

where:

op

is one of:

ADD

Add.

ADC

Add with Carry.

SUB

Subtract.

RSB

Reverse Subtract.

SBC

Subtract with Carry.

RSC

Reverse Subtract with Carry (ARM only).

S

is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation (see Conditional execution).

cond

is an optional condition code (see Conditional execution).

Rd

is the destination register.

Rn

is the register holding the first operand.

Operand2

is a flexible second operand. See Flexible second operand for details of the option. See also Wide constants.

Usage

The ADD instruction adds the values in Rn and Operand2.

The SUB instruction subtracts the value of Operand2 from the value in Rn.

The RSB (Reverse Subtract) instruction subtracts the value in Rn from the value of Operand2. This is useful because of the wide range of options for Operand2.

You can use ADC, SBC, and RSC to synthesize multiword arithmetic (see Multiword arithmetic examples).

The ADC (Add with Carry) instruction adds the values in Rn and Operand2, together with the carry flag.

The SBC (Subtract with Carry) instruction subtracts the value of Operand2 from the value in Rn. If the carry flag is clear, the result is reduced by one.

The RSC (Reverse Subtract with Carry) instruction subtracts the value in Rn from the value of Operand2. If the carry flag is clear, the result is reduced by one.

In certain circumstances, the assembler can substitute one instruction for another. Be aware of this when reading disassembly listings. See Instruction substitution for details.

Wide constants

In Thumb-2 ADD and SUB instructions, Operand2 can take any value in the range 0-4095, in addition to the normal range of Operand2 values. These wide constants cannot be used with RSB, ADC, SBC or RSC instructions.

You cannot use the S suffix with wide constants.

Use of r15 in Thumb-2 instructions

In most of these instructions, you cannot use r15 for Rd, or any operand.

The exception is that you can use r15 for Rn in ADD and SUB instructions, with a constant Operand2 value in the range 0-4095, and no S suffix. These instructions are useful for generating PC-relative addresses. Bit[1] of the PC value reads as 0 in this case, so that the base address for the calculation is always word-aligned.

See also SUBS PC, LR (Thumb-2 only).

Use of r15 in ARM instructions

If you use r15 as Rn, the value used is the address of the instruction plus 8.

If you use r15 as Rd:

  • Execution branches to the address corresponding to the result.

  • If you use the S suffix, the SPSR of the current mode is copied to the CPSR. You can use this to return from exceptions (see the Handling Processor Exceptions chapter in RealView Compilation Tools v2.2 Developer Guide).

Caution

Do not use the S suffix when using r15 as Rd in User mode or System mode. The effect of such an instruction is unpredictable (that is, it cannot be relied upon), but the assembler cannot warn you at assembly time.

You cannot use r15 for Rd or any operand in any data processing instruction that has a register-controlled shift (see Flexible second operand).

Condition flags

If S is specified, these instructions update the N, Z, C and V flags according to the result.

16-bit instructions

The following forms of these instructions are available in Thumb code, and are 16-bit instructions when used in Thumb-2 code:

ADDS Rd, Rn, #imm

imm range 0-7. Rd and Rn must both be Lo registers.

ADDS Rd, Rn, Rm

Rd, Rn and Rm must all be Lo registers.

ADD Rd, Rd, Rm

ARMv6 and earlier: either Rd or Rm, or both, must be a Hi register. ARMv6T2 and above: this restriction does not apply.

ADDS Rd, Rd, #imm

imm range 0-255. Rd must be a Lo register.

ADCS Rd, Rd, Rm

Rd, Rn and Rm must all be Lo registers.

ADD SP, SP, #imm

imm range 0-508, word aligned.

ADD Rd, SP, #imm

imm range 0-1020, word aligned. Rd must be a Lo register.

ADD Rd, PC, #imm

imm range 0-1020, word aligned. Rd must be a Lo register. Bits[1:0] of the PC are read as 0 in this instruction.

SUBS Rd, Rn, Rm

Rd, Rn and Rm must all be Lo registers.

SUBS Rd, Rn, #imm

imm range 0-7. Rd and Rn both Lo registers.

SUBS Rd, Rd, #imm

imm range 0-255. Rd must be a Lo register.

SBCS Rd, Rd, Rm

Rd, Rn and Rm must all be Lo registers.

SUB SP, SP, #imm

imm range 0-508, word aligned.

RSBS Rd, Rn, #0

Rd and Rn both Lo registers.

Architectures

These ARM instructions are available in all versions of the ARM architecture.

These 32-bit Thumb-2 instructions are available in T2 variants of ARMv6 and above.

These 16-bit Thumb instructions are available in all T variants of the ARM architecture.

Examples

    ADD     r2, r1, r3
    SUBS    r8, r6, #240        ; sets the flags on the result
    RSB     r4, r4, #1280       ; subtracts contents of r4 from 1280
    ADCHI   r11, r0, r3         ; only executed if C flag set and Z
                                ; flag clear
    RSCLES  r0,r5,r0,LSL r4     ; conditional, flags set

Incorrect example

    RSCLES  r0,r15,r0,LSL r4    ; r15 not permitted with register
                                ; controlled shift

Multiword arithmetic examples

These two instructions add a 64-bit integer contained in r2 and r3 to another 64-bit integer contained in r0 and r1, and place the result in r4 and r5.

    ADDS    r4, r0, r2    ; adding the least significant words
    ADC     r5, r1, r3    ; adding the most significant words

These instructions subtract one 96-bit integer from another:

    SUBS    r3, r6, r9
    SBCS    r4, r7, r10
    SBC     r5, r8, r11

For clarity, the above examples use consecutive registers for multiword values. There is no requirement to do this. The following, for example, is perfectly valid:

    SUBS    r6, r6, r9
    SBCS    r9, r2, r1
    SBC     r2, r8, r11
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