4.3.4. AND, ORR, EOR, BIC, and ORN

Logical AND, OR, Exclusive OR, Bit Clear, and OR NOT.

Syntax

op{S}{cond} Rd, Rn, Operand2

where:

op

is one of:

AND

logical AND.

ORR

logical OR.

EOR

logical Exclusive OR.

BIC

logical AND NOT.

ORN

logical OR NOT (Thumb-2 only).

S

is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation (see Conditional execution).

cond

is an optional condition code (see Conditional execution).

Rd

is the destination register.

Rn

is the register holding the first operand.

Operand2

is a flexible second operand. See Flexible second operand for details of the options.

Usage

The AND, EOR, and ORR instructions perform bitwise AND, Exclusive OR, and OR operations on the values in Rn and Operand2.

The BIC (Bit Clear) instruction performs an AND operation on the bits in Rn with the complements of the corresponding bits in the value of Operand2.

The ORN Thumb-2 instruction performs an OR operation on the bits in Rn with the complements of the corresponding bits in the value of Operand2.

In certain circumstances, the assembler can substitute BIC for AND, AND for BIC, ORN for ORR, or ORR for ORN. Be aware of this when reading disassembly listings. See Instruction substitution for details.

Use of r15 in Thumb-2 instructions

You cannot use r15 for Rd or any operand in any of these instructions.

Use of r15 in ARM instructions

If you use r15 as Rn, the value used is the address of the instruction plus 8.

If you use r15 as Rd:

  • Execution branches to the address corresponding to the result.

  • If you use the S suffix, the SPSR of the current mode is copied to the CPSR. You can use this to return from exceptions (see the Handling Processor Exceptions chapter in RealView Compilation Tools v2.2 Developer Guide).

Caution

Do not use the S suffix when using r15 as Rd in User mode or System mode. The effect of such an instruction is unpredictable, that is, it cannot be relied upon, but the assembler cannot warn you at assembly time.

You cannot use r15 for Rd or any operand in any data processing instruction that has a register-controlled shift (see Flexible second operand).

Condition flags

If S is specified, these instructions:

  • update the N and Z flags according to the result

  • can update the C flag during the calculation of Operand2 (see Flexible second operand)

  • do not affect the V flag.

16-bit instructions

The following forms of these instructions are available in Thumb code, and are 16-bit instructions when used in Thumb-2 code:

ANDS Rd, Rd, Rm

Rd and Rm must both be Lo registers.

EORS Rd, Rd, Rm

Rd and Rm must both be Lo registers.

ORRS Rd, Rd, Rm

Rd and Rm must both be Lo registers.

BICS Rd, Rd, Rm

Rd and Rm must both be Lo registers.

In the first three cases, it does not matter if you specify OPS Rd, Rm, Rd. The instruction is the same.

Architectures

These ARM instructions are available in all versions of the ARM architecture.

These 32-bit Thumb-2 instructions are available in T2 variants of ARMv6 and above.

These 16-bit Thumb instructions are available in all T variants of the ARM architecture.

ARM/Thumb-2 examples

    AND     r9,r2,#0xFF00
    ORREQ   r2,r0,r5
    EORS    r0,r0,r3,ROR r6
    ANDS    r9, r8, #0x19
    EORS    r7, r11, #0x18181818 
    BIC     r0, r1, #0xab
    ORN     r7, r11, r14, ROR #4
    ORNS    r7, r11, r14, ASR #32

Incorrect example

    EORS    r0,r15,r3,ROR r6    ; r15 not permitted with register
                                ; controlled shift
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