4.4.5. SMLALxy

Signed Multiply-Accumulate with 16-bit operands and a 64-bit accumulator.

Syntax

SMLAL<x><y>{cond} RdLo, RdHi, Rm, Rs

where:

<x>

is either B or T. B means use the bottom half (bits [15:0]) of Rm, T means use the top half (bits [31:16]) of Rm.

<y>

is either B or T. B means use the bottom half (bits [15:0]) of Rs, T means use the top half (bits [31:16]) of Rs.

cond

is an optional condition code (see Conditional execution).

RdHi, RdLo

are the destination registers. They also hold the accumulate value.

Rm, Rs

are the registers holding the values to be multiplied.

Usage

Do not use r15 for RdHi, RdLo, Rm, or Rs.

RdHi and RdLo must be different registers.

SMLALxy multiplies the signed integer from the selected half of Rs by the signed integer from the selected half of Rm, and adds the 32-bit result to the 64-bit value in RdHi and RdLo.

Condition flags

This instruction does not change the flags.

Note

SMLALxy cannot raise an exception. If overflow occurs on this instruction, the result wraps round without any warning.

Architectures

This ARM instruction is available in ARMv6 and above, and E variants of ARMv5.

This 32-bit Thumb-2 instruction is available in T2 variants of ARMv6 and above.

There is no 16-bit Thumb version of this instruction.

Examples

    SMLALTB     r2, r3, r7, r1
    SMLALBTVS   r0, r1, r9, r2

Incorrect example

    SMLALTT     r8, r9, r3, r15    ; use of r15 not permitted
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