4.4.9. SMLALD and SMLSLD

Dual 16-bit Signed Multiply with Addition or Subtraction of products and 64-bit Accumulation.

Syntax

op{X}{cond} RdLo, RdHi, Rm, Rs

where:

op

is one of:

SMLALD

Dual multiply, accumulate sum of products.

SMLSLD

Dual multiply, accumulate difference of products.

X

is an optional parameter. If X is present, the most and least significant halfwords of the second operand are exchanged before the multiplications occur.

cond

is an optional condition code (see Conditional execution).

RdLo, RdHi

are the destination registers for the 64-bit result. They also hold the 64-bit accumulate operand.

Rm, Rs

are the registers holding the operands.

Usage

Do not use r15 for any of RdLo, RdHi, Rm, or Rs.

Operation

SMLALD multiplies the bottom halfword of Rm with the bottom halfword of Rs, and the top halfword of Rm with the top halfword of Rs. It then adds both products to the value in RdLo, RdHi and stores the sum to RdLo, RdHi.

SMLSLD multiplies the bottom halfword of Rm with the bottom halfword of Rs, and the top halfword of Rm with the top halfword of Rs. It then subtracts the second product from the first, adds the difference to the value in RdLo, RdHi, and stores the result to RdLo, RdHi.

Condition flags

These instructions do not change the flags.

Architectures

These ARM instructions are available in ARMv6 and above, and E variants of ARMv5.

These 32-bit Thumb-2 instructions are available in T2 variants of ARMv6 and above.

There are no 16-bit Thumb versions of these instructions.

Examples

    SMLALD      r10, r11, r5, r1
    SMLSLD      r3, r0, r5, r1
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