### 4.4.7. SMMUL, SMMLA, and SMMLS

Signed Most significant word Multiply, with optional Accumulation
or Subtraction, with 32-bit operands and producing only the most
significant 32-bits of the result.

`op`

{R}{`cond`

} `Rd`

, `Rm`

, `Rs`

, `Rn`

where:

`op`

is one of:

`SMMUL`

Multiply, and truncate or round.

`SMMLA`

Multiply,
accumulate, and truncate or round.

`SMMLS`

Multiply,
subtract from `Rn`

,
and truncate or round.

`R`

is
an optional parameter. If `R`

is present, the
result is rounded, otherwise it is truncated.

`cond`

is an optional condition code (see *Conditional execution*).

`Rd`

is the destination register.

`Rm, Rs`

are the registers holding the operands.

`Rn`

is a register holding the value to be added or subtracted
from.

`SMMUL`

multiplies the values from `Rm`

and `Rs`

,
and stores the most significant 32 bits of the 64-bit result to `Rd`

.

`SMMLA`

multiplies the values from `Rm`

and `Rs`

,
adds the value in `Rn`

to
the most significant 32 bits of the product, and stores the result
in `Rd`

.

`SMMLS`

multiplies the values from `Rm`

and `Rs`

,
subtracts the product from the value in `Rn`

shifted
left by 32 bits, and stores the most significant 32 bits of the
result in `Rd`

.

If the optional `R`

parameter is specified, `0x80000000`

is
added before extracting the most significant 32 bits. This has the
effect of rounding the result.

Do not use r15 for any of `Rd`

, `Rm`

, `Rs`

,
or `Rn`

.

These instructions do not change the flags.

These ARM instructions are available in ARMv6 and above, and
E variants of ARMv5.

These 32-bit Thumb-2 instructions are available in T2 variants
of ARMv6 and above.

There are no 16-bit Thumb versions of these instructions.

SMMULGE r6, r4, r3
SMMULR r2, r2, r2