4.9.3. MRC, MRC2, MRRC and MRRC2

Move to ARM Register or Registers from Coprocessor.

Depending on the coprocessor, you might be able to specify various operations in addition.

Syntax

MRC{cond} coproc, opcode1, Rd, CRn, CRm{, opcode2}
MRC2 coproc, opcode1, Rd, CRn, CRm{, opcode2}
MRRC{cond} coproc, opcode1, Rd, Rn, CRm
MRRC2 coproc, opcode1, Rd, Rn, CRm

where:

cond

is an optional condition code (see Conditional execution).

coproc

is the name of the coprocessor the instruction is for. The standard name is pn, where n is an integer in the range 0 to 15.

opcode1

is a coprocessor-specific opcode.

Rd, Rn

are ARM source registers. Do not use r15 for Rd or Rn in MRRC or MRRC2.

In MRC and MRC2, if Rd is r15, only the flags field is affected.

CRn, CRm

are coprocessor registers.

opcode2

is an optional coprocessor-specific opcode.

Usage

The use of these instructions depends on the coprocessor. See the coprocessor documentation for details.

Note

MRC2 and MRRC2 are always unconditional.

Exceptions

Undefined Instruction.

Architectures

The MRC ARM instruction is available in all versions of the ARM architecture.

The MRC2 ARM instruction is available in ARMv5 and above.

The MRRC ARM instruction is available in ARMv6 and above, and E variants of ARMv5 excluding xP variants.

The MRRC2 ARM instruction is available in ARMv6 and above.

These 32-bit Thumb-2 instructions are available in T2 variants of ARMv6 and above.

There are no 16-bit Thumb versions of these instructions.

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