4.9.4. LDC and STC

Transfer Data between memory and Coprocessor.

Syntax

These instructions have three possible forms:

  • zero offset

  • pre-indexed offset

  • post-indexed offset.

The syntax of the three forms, in the same order, are:

op{L}{cond} coproc, CRd, [Rn]
op{L}{cond} coproc, CRd, [Rn, #{-}offset]{!}
op{L}{cond} coproc, CRd, [Rn], #{-}offset

where:

op

is either LDC or STC.

cond

is an optional condition code (see Conditional execution).

L

is an optional suffix specifying a long transfer.

coproc

is the name of the coprocessor the instruction is for. The standard name is pn, where n is an integer in the range 0 to 15.

CRd

is the coprocessor register to load or save.

Rn

is the register on which the memory address is based. If r15 is specified, the value used is the address of the current instruction plus eight.

-

is an optional minus sign. If - is present, the offset is subtracted from Rn. Otherwise, the offset is added to Rn.

offset

is an expression evaluating to a multiple of 4, in the range 0 to 1020.

!

is an optional suffix. If ! is present, the address including the offset is written back into Rn.

Usage

The use of these instructions depends on the coprocessor. See the coprocessor documentation for details.

Exceptions

Undefined Instruction. Data Abort.

Architectures

These ARM instructions are available in all versions of the ARM architecture.

These 32-bit Thumb-2 instructions are available in T2 variants of ARMv6 and above.

There are no 16-bit Thumb versions of these instructions.

Notes

Use of PC relative addressing in the STC instruction is deprecated in ARMv6T2.

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