4.8.1. B, BL, BX, BLX, and BXJ

Branch, Branch with Link, Branch and exchange instruction set, Branch with Link and exchange instruction set, Branch and change to Jazelle state.

Syntax

op{cond}{.W} label
op{cond} Rm

where:

op

is one of:

B

Branch.

BL

Branch with link.

BX

Branch and exchange instruction set.

BLX

Branch with link, and exchange instruction set.

BXJ

Branch, and change to Jazelle execution.

cond

is an optional condition code (see Conditional execution). cond is not available on all forms of this instruction, see Instruction availability and branch ranges.

.W

is an optional instruction width specifier to force the use of a 32-bit B instruction in Thumb-2. See B in Thumb-2 for details.

label

is a program-relative expression. See Register-relative and program-relative expressions for more information.

Rm

is a register containing an address to branch to.

Operation

All these instructions cause a branch to label, or to the address contained in Rm. In addition:

  • The BL and BLX instructions copy the address of the next instruction into r14 (lr, the link register).

  • The BX and BLX instructions can change the processor state from ARM to Thumb, or from Thumb to ARM.

    BLX label always changes the state.

    BX Rm and BLX Rm derive the target state from bit[0] of Rm:

    • if bit[0] of Rm is 0, the processor changes to, or remains in, ARM state

    • if bit[0] of Rm is 1, the processor changes to, or remains in, Thumb state.

  • The BXJ instruction changes the processor state to Jazelle.

Instruction availability and branch ranges

Table 4.2 shows the instructions that are available in ARM and Thumb state. Instructions that are not shown in this table are not available. Notes in brackets show the first architecture version where the instruction is available.

Table 4.2. Branch instruction availability and range

InstructionARM 16-bit Thumb32-bit Thumb-2
B label±32MB(All)±2KB(All T)±16MB[1]
B{cond} label±32MB(All)–252 to +258(All T)±1MBa
B RmUse BX Rm Use BX Rm Use 16-bit BX Rm
B{cond} RmUse BX{cond} Rm- -
BL label±32MB(All)±4MB[2](All T)±16MB
BL{cond} label±32MB(All)- -
BL RmUse BLX RmUse BLX Rm Use 16-bit BLX Rm
BL{cond} RmUse BLX{cond} Rm- -
BX RmAvailable(4T, 5)Available(All T)Use 16-bit
BX{cond} RmAvailable(4T, 5)- -
BLX label±32MB(5)±4MB[3](5T)±16MB
BLX RmAvailable(5)Available(5T)Use 16-bit
BLX{cond} RmAvailable(5)- -
BXJ RmAvailable(5J, 6)- Available
BXJ{cond} RmAvailable(5J, 6)- -

[1] Use .W to instruct the assembler to use this 32-bit instruction.

[2] This is an instruction pair.

[3] This is an instruction pair.

Extending branch ranges

Machine-level B and BL instructions have restricted ranges from the address of the current instruction. However, you can use these instructions even if label is out of range. Often you do not know where the linker places label. When necessary, the linker adds code to enable longer branches (see the chapter describing basic linker functionality in RealView Compilation Tools v2.2 Linker and Utilities Guide). The added code is called a veneer.

B in Thumb-2

You can use the .W width specifier to force B to generate a 32-bit instruction in Thumb-2 code.

B.W always generates a 32-bit instruction, even if the target could be reached using a 16-bit instruction.

For forward references, B without .W always generates a 16-bit instruction in Thumb code, even if that results in failure for a target that could be reached using a 32-bit Thumb-2 instruction.

Condition flags

These instructions do not change the flags.

Architectures

See Instruction availability and branch ranges for details of availability of these instructions in each architecture.

Examples

    B       loopA
    BLE     ng+8
    BL      subC
    BLLT    rtX
    BEQ     {pc}+4  ; #0x8004
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