4.2.11. SRS

Store Return State.

Syntax

SRS{addr_mode}{cond} r13{!}, #modenum

where:

addr_mode

is any one of the following:

IA

Increment address After each transfer

IB

Increment address Before each transfer (ARM only)

DA

Decrement address After each transfer (ARM only)

DB

Decrement address Before each transfer.

cond

is an optional condition code (see Conditional execution).

Note

This is an unconditional instruction in ARM. cond is only allowed in Thumb-2 code, using a preceding IT instruction.

!

is an optional suffix. If ! is present, the final address is written back into the r13 of the mode specified by modenum.

modenum

specifies the number of the mode whose banked r13 is used as the base register, see Processor mode.

Operation

SRS stores the r14 and the SPSR of the current mode, at the address contained in r13 of the mode specified by modenum, and the following word respectively. Optionally updates r13 of the mode specified by modenum. This is compatible with the normal use of the STM instruction for stack accesses, see LDM and STM.

Usage

You can use SRS to store return state for an exception handler on a different stack from the one automatically selected.

Exceptions

Data Abort.

Notes

Where addresses are not word-aligned, SRS ignores the least significant two bits of the specified address.

The time order of the accesses to individual words of memory generated by SRS is not architecturally defined. Do not use this instruction on memory-mapped I/O locations where access order matters.

SRS is unpredictable in User and System modes (that is, it cannot be relied upon), because they do not have SPSRs.

Architectures

This ARM instruction is available in ARMv6 and above.

This 32-bit Thumb-2 instruction is available in T2 variants of ARMv6 and above.

There is no 16-bit version of this instruction.

Example

R13_usr  EQU 16
         SRSFD   #R13_usr

Incorrect examples

    SRSFD   #32!        ; there is no mode 32
    SRSEQFD #R13_usr    ; SRS is always unconditional
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