4.9.2. MCR, MCR2, MCRR, and MCRR2

Move to Coprocessor from ARM Register or Registers. Depending on the coprocessor, you might be able to specify various operations in addition.

Syntax

MCR{cond} coproc, opcode1, Rd, CRn, CRm{, opcode2}
MCR2 coproc, opcode1, Rd, CRn, CRm{, opcode2}
MCRR{cond} coproc, opcode1, Rd, Rn, CRm
MCRR2 coproc, opcode1, Rd, Rn, CRm

where:

cond

is an optional condition code (see Conditional execution).

coproc

is the name of the coprocessor the instruction is for. The standard name is pn, where n is an integer in the range 0 to 15.

opcode1

is a coprocessor-specific opcode.

Rd, Rn

are ARM source registers. Do not use r15 for Rd or Rn.

CRn, CRm

are coprocessor registers.

opcode2

is an optional coprocessor-specific opcode.

Usage

The use of these instructions depends on the coprocessor. See the coprocessor documentation for details.

Note

MCR2 and MCRR2 are always unconditional in ARM state.

Exceptions

Undefined Instruction.

Architectures

The MCR ARM instruction is available in all versions of the ARM architecture.

The MCR2 ARM instruction is available in ARMv5 and above.

The MCRR ARM instruction is available in ARMv6 and above, and E variants of ARMv5 excluding xP variants.

The MCRR2 ARM instruction is available in ARMv6 and above.

These 32-bit Thumb-2 instructions are available in T2 variants of ARMv6 and above.

There are no 16-bit Thumb versions of these instructions.

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