4.2.4. LDR and STR (register or pre-indexed register offset)

Load and Store register. Byte and halfword loads are zero-extended or sign-extended to 32 bits.


op{type}{cond} {Rd, {Rd2,}} [Rn, +/-Rm {, shift}]{!}



can be either:


Load Register


Store Register.


can be any one of:


unsigned Byte


Signed Byte (LDR only)


unsigned Halfword


Signed Halfword (LDR only)


omitted, for Word




is an optional condition code (see Conditional execution).


is the ARM register to load or save.


is the second ARM register to load or save (type == D only).


is the register on which the memory address is based.


is a register containing a value to be used as the offset. Rm must not be r15.


is an optional shift. See Operation and restrictions for details.


is an optional suffix. If ! is present, the instruction is a pre-indexed instruction, and Rn must not be the same register as Rd or Rd2.

Operation and restrictions

In ARM, the value in Rm is added to or subtracted from the value in Rn. In Thumb and Thumb-2, subtraction is not allowed. The result is used as the memory address for the transfer. If the instruction is a pre-indexed instruction, the result is written back into Rn.

The range of shifts allowed is:

  • LSL 0 to 3 for all Thumb-2 instructions except Doubleword

  • Any one of the following for ARM Word and unsigned Byte instructions:

    • LSL 0 to 31

    • LSR 1 to 32

    • ASR 1 to 32

    • ROR 1 to 31

    • RRX

  • No shift is allowed for Thumb-2 Doubleword instructions, or for ARM Signed Byte, unsigned Halfword, Signed halfword, or Doubleword instructions.

Doubleword register restrictions

For Thumb-2 instructions, you must not specify r15 for either Rd or Rd2.

For ARM instructions:

  • Rd must be an even-numbered register

  • Rd must not be r14

  • Rd2 must be R(d + 1).

16-bit instructions

16-bit versions of a subset of these instructions are available in Thumb-2 code, and in Thumb code on other Thumb-capable processors.

The following restrictions apply to 16-bit instructions:

  • Only register offset instructions are available. Pre-indexed register offset instructions are not available.

  • Rd, Rn, and Rm must all be Lo registers.

  • Word, unsigned Halfword, Signed Halfword, unsigned Byte and Signed Byte instructions are available. Doubleword instructions are not available.

Loading to r15

Rd can be the PC, in either ARM or Thumb-2 code. In this case, type must be omitted.

A load to r15 (pc) causes a branch to the instruction at the address loaded.

In ARMv4, bits[1:0] of the value loaded must be zero.

In ARMv5 and above:

  • bits[1:0] of a value loaded to r15 must not have the value 0b10

  • if bit[0] of a value loaded to r15 is set, the processor changes to Thumb state.

You cannot use the T suffix when loading to r15.

Saving from r15

In Thumb code, you cannot save from r15.

In ARM code, avoid saving from r15 if possible.

If you do save from r15, the value saved is the address of the current instruction, plus an implementation-defined constant. The constant is always the same for a particular processor.

If your assembled code might be used on different processors, you can find out what the constant is at runtime using code like the following:

    SUB R1, PC, #4 ; R1 = address of following STR instruction
    STR PC, [R0]   ; Store address of STR instruction + offset,
    LDR R0, [R0]   ; then reload it
    SUB R0, R0, R1 ; Calculate the offset as the difference

If your code is to be assembled for a particular processor, the value of the constant is available in armasm as {PCSTOREOFFSET}.


The ARM instructions are available in all versions of the ARM architecture.

The 32-bit Thumb-2 instructions are available in all T2 variants of the ARM architecture.

The 16-bit Thumb instructions are available in all T variants of the ARM architecture.

In T and T2 variants of ARMv5 and above:

  • in ARM state, a load to r15 causes a change to Thumb state if bit[0] of the value loaded is 1

  • in Thumb state, a load to r15 causes a change to ARM state if bit[0] of the value loaded is 0.

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