4.5.2. QADD, QSUB, QDADD, and QDSUB

Signed Add, Subtract, Double and Add, Double and Subtract, saturating the result to the signed range –231 = x = 231–1.

See also Parallel add and subtract.

Syntax

op{cond} Rd, Rm, Rn

where:

op

is one of QADD, QSUB, QDADD, or QDSUB.

cond

is an optional condition code (see Conditional execution).

Rd

is the destination register.

Rm, Rn

are the registers holding the operands.

Do not use r15 for Rd, Rm, or Rn.

Usage

The QADD instruction adds the values in Rm and Rn.

The QSUB instruction subtracts the value in Rn from the value in Rm.

The QDADD instruction calculates SAT(Rm + SAT(Rn * 2)). Saturation can occur on the doubling operation, on the addition, or on both. If saturation occurs on the doubling but not on the addition, the Q flag is set but the final result is unsaturated.

The QDSUB instruction calculates SAT(Rm - SAT(Rn * 2)). Saturation can occur on the doubling operation, on the subtraction, or on both. If saturation occurs on the doubling but not on the subtraction, the Q flag is set but the final result is unsaturated.

Note

All values are treated as two’s complement signed integers by these instructions.

See also Parallel add and subtract for similar parallel instructions, available in ARMv6 and above only.

Condition flags

If saturation occurs, these instructions set the Q flag. To read the state of the Q flag, use an MRS instruction (see MRS).

No other flags are affected.

Architectures

These ARM instructions are available in ARMv6 and above, and E variants of ARMv5.

These 32-bit Thumb-2 instructions are available in T2 variants of ARMv6 and above.

There are no 16-bit Thumb versions of these instructions.

Examples

    QADD    r0, r1, r9
    QDSUBLT r9, r0, r1

Incorrect examples

    QSUBS   r3, r4, r2    ; use of S suffix not permitted
    QDADD   r11, r15, r0  ; use of r15 not permitted
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