4.3.7. CMP and CMN

Compare and Compare Negative.

Syntax

CMP{cond} Rn, Operand2
CMN{cond} Rn, Operand2

where:

cond

is an optional condition code (see Conditional execution).

Rn

is the ARM register holding the first operand.

Operand2

is a flexible second operand. See Flexible second operand for details of the options.

Usage

These instructions compare the value in a register with Operand2. They update the condition flags on the result, but do not place the result in any register.

The CMP instruction subtracts the value of Operand2 from the value in Rn. This is the same as a SUBS instruction, except that the result is discarded.

The CMN instruction adds the value of Operand2 to the value in Rn. This is the same as an ADDS instruction, except that the result is discarded.

In certain circumstances, the assembler can substitute CMN for CMP, or CMP for CMN. Be aware of this when reading disassembly listings. See Instruction substitution for details.

Use of r15 in ARM instructions

If you use r15 as Rn, the value used is the address of the instruction plus 8.

You cannot use r15 for any operand in any data processing instruction that has a register-controlled shift (see Flexible second operand).

Use of r15 in Thumb-2 instructions

You cannot use r15 for any operand in these instructions.

Condition flags

These instructions update the N, Z, C and V flags according to the result.

16-bit instructions

The following forms of these instructions are available in Thumb code, and are 16-bit instructions when used in Thumb-2 code:

CMP Rn, Rm

Rn and Rm can both be Lo or Hi registers.

CMN Rn, Rm

Rn and Rm must both be Lo registers.

CMP Rn, #imm

Rn must be a Lo register. imm range 0-255.

Architectures

These ARM instructions are available in all versions of the ARM architecture.

These 32-bit Thumb-2 instructions are available in T2 variants of ARMv6 and above.

These 16-bit Thumb instructions are available in all T variants of the ARM architecture.

Examples

    CMP     r2, r9
    CMN     r0, #6400
    CMPGT   r13, r7, LSL #2

Incorrect example

    CMP     r2, r15, ASR r0 ; r15 not permitted with register controlled shift
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