4.4.1. MUL, MLA, and MLS

Multiply, Multiply-Accumulate, and Multiply-Subtract, with signed or unsigned 32-bit operands, giving the least significant 32 bits of the result.

Syntax

MUL{S}{cond} Rd, Rm, Rs
MLA{S}{cond} Rd, Rm, Rs, Rn
MLS{cond} Rd, Rm, Rs, Rn

where:

cond

is an optional condition code (see Conditional execution).

S

is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation (see Conditional execution).

You cannot use S in a Thumb-2 MLA instruction.

You can only use S in a Thumb-2 MUL instruction if Rd and Rm are the same register, and all operands are low registers. This is a 16-bit instruction.

Rd

is the destination register.

Rm, Rs

are registers holding the values to be multiplied.

Rn

is a register holding the value to be added or subtracted from.

Usage

The MUL instruction multiplies the values from Rm and Rs, and places the least significant 32 bits of the result in Rd.

The MLA instruction multiplies the values from Rm and Rs, adds the value from Rn, and places the least significant 32 bits of the result in Rd.

The MLS instruction multiplies the values from Rm and Rs, subtracts the result from the value from Rn, and places the least significant 32 bits of the final result in Rd.

Do not use r15 for Rd, Rm, Rs, or Rn.

Condition flags

If S is specified, the MUL and MLA instructions:

  • update the N and Z flags according to the result

  • corrupt the C and V flag in ARMv4 and earlier

  • do not affect the C or V flag in ARMv5 and above.

16-bit instructions

The following form of the MUL instruction is available in Thumb code, and is a 16-bit instruction when used in Thumb-2 code:

MULS Rd, Rd, Rs

Rd and Rs must both be Lo registers.

Architectures

The MUL and MLA ARM instructions are available in all versions of the ARM architecture.

The MLS ARM instruction is available in T2 variants of ARMv6 and above.

These Thumb-2 instructions are available in T2 variants of ARMv6 and above.

The MULS Thumb instruction is available in all T variants of the ARM architecture.

Examples

    MUL     r10, r2, r5
    MLA     r10, r2, r1, r5
    MULS    r0, r2, r2
    MULLT   r2, r3, r2
    MLS     r4, r5, r6, r7

Incorrect example

    MUL     r15, r0, r3   ; use of r15 not permitted
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