4.2.10. RFE

Return From Exception.

Syntax

RFE{addr_mode}{cond} Rn{!}

where:

addr_mode

is any one of the following:

IA

Increment address After each transfer (Full Descending stack)

IB

Increment address Before each transfer (ARM only)

DA

Decrement address After each transfer (ARM only)

DB

Decrement address Before each transfer.

cond

is an optional condition code (see Conditional execution).

Note

This is an unconditional instruction in ARM. cond is only allowed in Thumb-2 code, using a preceding IT instruction.

Rn

specifies the base register. Do not use r15 for Rn.

!

is an optional suffix. If ! is present, the final address is written back into Rn.

Usage

You can use RFE to return from an exception if you previously saved the return state using the SRS instruction (see SRS).

Operation

Loads the PC and the CPSR from the address contained in Rn, and the following address. Optionally updates Rn.

Exceptions

Data Abort.

Notes

RFE writes an address to the PC. The alignment of this address must be correct for the instruction set in use after the exception return:

  • For a return to ARM, the address written to the PC must be word-aligned.

  • For a return to Thumb-2, the address written to the PC must be halfword-aligned.

  • For a return to Jazelle®, there are no alignment restrictions on the address written to the PC.

The results of breaking these rules are unpredictable, that is, the results cannot be relied upon. However, no special precautions are required in software, if the instructions are used to return after a valid exception entry mechanism.

Where addresses are not word-aligned, RFE ignores the least significant two bits of Rn.

The time order of the accesses to individual words of memory generated by RFE is not architecturally defined. Do not use this instruction on memory-mapped I/O locations where access order matters.

If User mode is specified by mode, the usual rules apply about writing to CPSR (see ARM Architecture Reference Manual for details).

If Monitor mode is specified by mode, the result is unpredictable, that is, it cannot be relied upon (see SMI).

Architectures

This ARM instruction is available in ARMv6 and above.

This 32-bit Thumb-2 instruction is available in T2 variants of ARMv6 and above.

There is no 16-bit version of this instruction.

Example

    RFE r13!

Incorrect example

    RFEFD   r15     ; do not use r15
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