4.10.3. MRS

Move the contents of the CPSR or SPSR to a general-purpose register.


MRS{cond} Rd, psr



is an optional condition code (see Conditional execution).


is the destination register. Rd must not be r15.


is either CPSR or SPSR.


Use MRS in combination with MSR as part of a read-modify-write sequence for updating a PSR, for example to change processor mode, or to clear the Q flag.

In process swap code, the programmer's model state of the process being swapped out must be saved, including relevant PSR contents. Similarly, the state of the process being swapped in must also be restored. These operations make use of MRS/store and load/MSR instruction sequences.


You must not attempt to access the SPSR when the processor is in User or System mode. This is your responsibility. The assembler cannot warn you about this because it does not know in what processor mode the code will be executed.

If you do this, the result is unpredictable, that is, it cannot be relied upon.

The CPSR execution state bits can only be read when the processor is in Debug state, halting debug-mode. Otherwise, the execution state bits in the CPSR read as zero.

Condition flags

This instruction does not change the flags.


This ARM instruction is available in all versions of the ARM architecture.

This 32-bit Thumb-2 instruction is available in T2 variants of ARMv6 and above.

There is no 16-bit Thumb version of this instruction.

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