4.7.3. PKHBT and PKHTB

Halfword Packing instructions.

Combine a halfword from one register with a halfword from another register. One of the operands can be shifted before extraction of the halfword.

Syntax

op{cond} Rd, Rn, Rm{, shift}

where:

op

is one of:

PKHBT

Combines bits[15:0] of Rn with bits[31:16] of the shifted value from Rm.

PKHTB

Combines bits[31:16] of Rn with bits[15:0] of the shifted value from Rm.

cond

is an optional condition code (see Conditional execution).

Rd

is the destination register.

Rn

is the register holding the first operand.

Rm

is the register holding the first operand.

shift

is one of:

LSL #n

Logical Shift Left. n is in the range 0 to 31. Only available for PKHBT.

ASR #n

Arithmetic Shift Right. n is in the range 1 to 32. Only available for PKHTB.

Do not use r15 for Rd, Rn, or Rm.

Condition flags

These instructions do not change the flags.

Architectures

These ARM instructions are available in ARMv6 and above.

These 32-bit Thumb-2 instructions are available in T2 variants of ARMv6 and above.

There are no 16-bit Thumb versions of these instructions.

Examples

    PKHBT   r0, r3, r5          ; combine the bottom halfword of r3 with the top halfword of r5
    PKHBT   r0, r3, r5, LSL #16 ; combine the bottom halfword of r3 with the bottom halfword of r5
    PKHTB   r0, r3, r5, ASR #16 ; combine the top halfword of r3 with the top halfword of r5

You can also scale the second operand by using different values of shift.

Incorrect examples

    PKHBT   r4, r15, r1         ; use of r15 not permitted
    PKHBTEQ r4, r5, r1, ASR #8  ; ASR not permitted with PKHBT
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