4.2.6. LDR (PC-relative)

Load register. The address is an offset from the PC. Byte and halfword loads are zero-extended or sign-extended to 32 bits.

Syntax

LDR{type}{cond}{.W} Rd, {Rd2,} label

where:

type

can be any one of:

B

unsigned Byte

SB

Signed Byte (LDR only)

H

unsigned Halfword

SH

Signed Halfword (LDR only)

-

omitted, for Word

D

Doubleword.

cond

is an optional condition code (see Conditional execution).

.w

is an optional instruction width specifier. See LDR (PC-relative) in Thumb-2 for details.

Rd

is the ARM register to load or save.

Rd2

is the second ARM register to load or save (type == D only).

label

is a program-relative expression. See Register-relative and program-relative expressions for more information.

label must be within ±4KB of the current instruction.

Usage

The assembler calculates the offset from the PC for you. The assembler generates an error if label is out of range.

LDR (PC-relative) in Thumb-2

You can use the .W width specifier to force LDR to generate a 32-bit instruction in Thumb-2 code.

LDR.W always generates a 32-bit instruction, even if the target could be reached using a 16-bit LDR.

For forward references, LDR without .W always generates a 16-bit instruction in Thumb code, even if that results in failure for a target that could be reached using a 32-bit Thumb-2 LDR instruction.

Doubleword register restrictions

For Thumb-2 instructions, you must not specify r15 for either Rd or Rd2.

For ARM instructions:

  • Rd must be an even-numbered register

  • Rd must not be r14

  • Rd2 must be R(d + 1).

16-bit instruction

A 16-bit version of this instruction is available in Thumb-2 code, and in Thumb code on Thumb-capable processors conforming to ARMv6 and earlier.

The following restrictions apply to the 16-bit instruction:

  • Rd must be a Lo register

  • type must be omitted, that is, only Load Word is available

  • offset must be in the range 0 to +1020, and must be divisible by 4.

Loading to r15

Rd can be the PC, in either ARM or Thumb-2 code. In this case, type must be omitted.

A load to r15 (pc) causes a branch to the instruction at the address loaded.

In ARMv4, bits[1:0] of the value loaded must be zero.

In ARMv5 and above:

  • bits[1:0] of a value loaded to r15 must not have the value 0b10

  • if bit[0] of a value loaded to r15 is set, the processor changes to Thumb state.

You cannot use the T suffix when loading to r15.

Architectures

This ARM instruction is available in all versions of the ARM architecture.

This 32-bit Thumb-2 instruction is available in all T2 variants of the ARM architecture.

This 16-bit Thumb instruction is available in all T variants of the ARM architecture.

In T and T2 variants of ARMv5 and above:

  • in ARM state, a load to r15 causes a change to Thumb state if bit[0] of the value loaded is 1

  • in Thumb state, a load to r15 causes a change to ARM state if bit[0] of the value loaded is 0.

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