4.4.6. SMUAD{X} and SMUSD{X}

Dual 16-bit Signed Multiply with Addition or Subtraction of products, and optional exchange of operand halves.

Syntax

op{X}{cond} Rd, Rm, Rs

where:

op

is one of:

SMUAD

Dual multiply, add products.

SMUSD

Dual multiply, subtract products.

X

is an optional parameter. If X is present, the most and least significant halfwords of the second operand are exchanged before the multiplications occur.

cond

is an optional condition code (see Conditional execution).

Rd

is the destination register.

Rm, Rs

are the registers holding the operands.

Operation

Do not use r15 for any of Rd, Rm, or Rs.

SMUAD multiplies the bottom halfword of Rm with the bottom halfword of Rs, and the top halfword of Rm with the top halfword of Rs. It then adds the products and stores the sum to Rd.

SMUSD multiplies the bottom halfword of Rm with the bottom halfword of Rs, and the top halfword of Rm with the top halfword of Rs. It then subtracts the second product from the first, and stores the difference to Rd.

Condition flags

These instructions do not change the flags.

The SMUAD instruction sets the Q flag if the addition overflows.

Architectures

These ARM instructions are available in ARMv6 and above, and E variants of ARMv5.

These 32-bit Thumb-2 instructions are available in T2 variants of ARMv6 and above.

There are no 16-bit Thumb versions of these instructions.

Examples

    SMUAD       r2, r3, r2
    SMUSDXNE    r0, r1, r2
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