### 4.3.13. ASR, LSL, LSR, ROR, and RRX

Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with Extend.

These instructions are synonyms for `MOV` instructions with shifted register second operands.

#### Syntax

````op`{S}{`cond`} `Rd`, `Rm`, `Rs`
```
````op`{S}{`cond`} `Rd`, `Rm`, #`sh`
```
```RRX{S}{`cond`} `Rd`, `Rm`
```

where:

`op`

is one of `ASR`, `LSL`, `LSR`, or `ROR`.

`S`

is an optional suffix. If `S` is specified, the condition code flags are updated on the result of the operation (see Conditional execution).

`Rd`

is the destination register.

`Rm`

is the register holding the first operand. This operand is shifted right.

`Rs`

is a register holding a shift value to apply to the value in `Rm`. Only the least significant byte is used.

`sh`

is a constant shift. The range of values permitted depends on the instruction:

`ASR`

allowed shifts 1-32

`LSL`

allowed shifts 0-31

`LSR`

allowed shifts 1-32

`ROR`

allowed shifts 1-31.

#### Usage

`ASR` provides the signed value of the contents of a register divided by a power of two. It copies the sign bit into vacated bit positions on the left.

`LSL` provides the value of a register multiplied by a power of two. `LSR` provides the unsigned value of a register divided by a variable power of two. Both instructions insert zeros into the vacated bit positions.

`ROR` provides the value of the contents of a register rotated by a value. The bits that are rotated off the right end are inserted into the vacated bit positions on the left.

`RRX` provides the value of the contents of a register shifted right one bit. The old carry flag is shifted into bit[31]. If the `S` suffix is present, the old bit[0] is placed in the carry flag.

#### Condition flags

If `S` is specified, these instructions update the N and Z flags according to the result.

The C flag is unaffected if the shift value is 0. Otherwise, the C flag is updated to the last bit shifted out.

#### 16-bit instructions

The following forms of these instructions are available in Thumb code, and are 16-bit instructions when used in Thumb-2 code:

```ASRS Rd, Rm, #sh```

`Rd` and `Rm` must both be Lo registers. Allowed shifts 1-32.

`ASRS Rd, Rm, Rs`

`Rd`, `Rm`, and `Rs` must all be Lo registers.

```LSLS Rd, Rm, #sh```

`Rd` and `Rm` must both be Lo registers. Allowed shifts 0-31.

`LSLS Rd, Rm, Rs`

`Rd`, `Rm`, and `Rs` must all be Lo registers.

```LSRS Rd, Rm, #sh```

`Rd` and `Rm` must both be Lo registers. Allowed shifts 1-32.

`LSRS Rd, Rm, Rs`

`Rd`, `Rm`, and `Rs` must all be Lo registers.

`RORS Rd, Rm, Rs`

`Rd`, `Rm`, and `Rs` must all be Lo registers.

#### Architectures

These ARM instructions are available in all versions of the ARM architecture.

These 32-bit Thumb-2 instructions are available in T2 variants of ARMv6 and above.

These 16-bit Thumb instructions are available in all T variants of the ARM architecture.

#### Examples

```    ASR     r7, r8, r9
LSL     r1, r2, r3
LSLS    r1, r2, r3
LSR     r4, r5, r6
LSRS    r4, r5, r6
ROR     r4, r5, r6
RORS    r4, r5, r6
```