4.3.5. BFC and BFI

Bit Field Clear and Bit Field Insert. Clear adjacent bits in a register, or Insert adjacent bits from one register into another.

Syntax

BFC{cond} Rd, #lsb, #width
BFI{cond} Rd, Rn, #lsb, #width

where:

cond

is an optional condition code (see Conditional execution).

Rd

is the destination register. Rd must not be r15.

Rn

is the source register. Rn must not be r15.

lsb

is the least significant bit that is to be cleared or copied.

width

is the number of bits to be cleared or copied. width must not be 0, and (width+lsb) must be less than 32.

BFC

width bits in Rd are cleared, starting at lsb. Other bits in Rd are unchanged.

BFI

width bits in Rd, starting at lsb, are replaced by width bits from Rn, starting at bit[0]. Other bits in Rd are unchanged.

Condition flags

These instructions do not change the flags.

Architectures

These ARM instructions are available in ARMv6T2 and above.

These 32-bit Thumb-2 instructions are available in T2 variants of ARMv6 and above.

There are no 16-bit Thumb versions of these instructions.

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