2.11. Assembly language changes

Table 2.10 shows the main differences between the RVCT v2.2 and earlier versions of the ARM assembly language. The old ARM syntax is still accepted by the assembler.

Table 2.10. Changes from earlier ARM assembly language

ChangeOld ARM syntaxPreferred syntax
The default addressing mode for LDM and STM is IA


LDMIASTMIA

LDM, STM
You can use the PUSH and POP mnemonics for full, descending stack operations in ARM as well as Thumb.


STMFD sp!, {reglist}
LDMFD sp!, {reglist}


PUSH {reglist}
POP {reglist}

You can use the LSL, LSR, ASR, ROR, and RRX instruction mnemonics for instructions with rotations and no other operation, in ARM as well as Thumb.


MOV RdRn, LSL shift
MOV RdRn, LSR shift
MOV RdRn, ASR shift
MOV RdRn, ROR shift
MOV RdRn, RRX


LSL RdRnshift
LSR RdRnshift
ASR RdRnshift
ROR RdRnshift
RRX RdRn

Use the label form for PC-relative addressing. Do not use the offset form in new code.


LDR Rd, [pc, #offset]


LDR Rdlabel

Specify both registers for doubleword memory accesses. You must still obey rules about the register combinations you can use.


LDRD Rdaddr_mode


LDRD RdRd2addr_mode

{cond}, if used, is always the last element of all instructions.


ADD{cond}S
LDR{cond}SB


ADDS{cond}
LDRSB{cond}

You can use both ARM {cond} conditional forms and Thumb-2 IT instructions, in both ARM and Thumb-2 code. The assembler checks for consistency between the two, and assembles the appropriate code depending on the current instruction set.


ADDEQ r1, r2, r3
LDRNE r1, [r2, r3]


ITEQ TE
ADDEQ r1, r2, r3
LDRNE r1, [r2, r3]

In addition, some flexibility is permitted in RVCT v2.2 that was not permitted in previous assemblers (see Table 2.11).

Table 2.11. Relaxation of requirements

RelaxationPreferred syntaxPermitted syntax
If the destination register is the same as the first operand, you can use a two register form of the instruction.


ADD r1, r1, r3


ADD r1, r3

In RVCT v2.2, you can write source code for Thumb processors using the ARM assembly language.

If you are writing Thumb code for a pre-Thumb-2 processor, you must restrict yourself to instructions that are available on the processor. The assembler generates error messages if you attempt to use an instruction that is not available.

If you are writing Thumb code for a Thumb-2 processor, you can minimize your code size by using 16-bit instructions wherever possible.

Table 2.12 shows the main differences between Thumb assembly language and ARM assembly language. The assembler accepts the old Thumb syntax only if it is preceded by a CODE16 directive, or if the source file is assembled with the --16 command-line option.

Table 2.12. Differences between ARM and Thumb assembly language

ChangeOld Thumb syntaxARM syntax
The default addressing mode for LDM and STM is IALDMIA, STMIALDM, STM
You must use the S postfix on instructions that update the flags. This change is essential to avoid conflict with 32-bit Thumb-2 instructions.


ADD r1, r2, r3
SUB r4, r5, #6


ADDS r1, r2, r3
SUBS r4, r5, #6

The preferred form for ALU instructions specifies three registers, even if the destination register is the same as the first operand.


ADD r7, r8
SUB r1, #80


ADD r7, r7, r8
SUBS r1, r1, #80

If Rd and Rn are both Lo registers, MOV Rd, Rn is disassembled as ADDS Rd, Rn, #0.


MOV r2r3
MOV r8r9
CPY r0r1
LSL r2r3, #0


ADDS r2r3, #0
MOV r8r9
MOV r0r1
MOVS r2r3

NEG Rd, Rm is disassembled as RSBS Rd, Rm, #0.NEG Rd, RmRSBS Rd, Rm, #0
NOP instructions replace MOV r8, r8 when available.- NOPNOP MOV r8, r8
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