Glossary

The items in this glossary are listed in alphabetical order, with any symbols and numerics appearing at the end.

AAPCS

See Procedure Call Standard for The ARM Architecture.

ABI for the ARM Architecture (base standard) (BSABI)

The ABI for the ARM Architecture is a collection of specifications, some open and some specific to ARM architecture, that regulate the inter-operation of binary code in a range of ARM architecture-based execution environments. The base standard specifies those aspects of code generation that must be standardized to support inter-operation and is aimed at authors and vendors of C and C++ compilers, linkers, and runtime libraries.

American National Standards Institute (ANSI)

An organization that specifies standards for, among other things, computer software. This is superseded by the International Standards Organization.

ANSI

See American National Standards Institute.

Architecture

The term used to identify a group of processors that have similar characteristics.

ARM instruction

A word that encodes an operation for an ARM processor operating in ARM state. ARM instructions must be word-aligned.

ARM state

A processor that is executing ARM instructions is operating in ARM state. The processor switches to Thumb state (and to recognizing Thumb instructions) when directed to do so by a state-changing instruction such as BX, BLX.

See Also Thumb state.

Big-endian

Memory organization where the least significant byte of a word is at a higher address than the most significant byte.

Byte

A unit of memory storage consisting of eight bits.

Canonical Frame Address (CFA)

In DWARF, this is an address on the stack specifying where the call frame of an interrupted function is located.

CFA

See Canonical Frame Address.

Coprocessor

An additional processor that is used for certain operations. Usually used for floating-point math calculations, signal processing, or memory management.

CPSR

See Current Processor Status Register.

Current Processor Status Register (CPSR)

A register containing the current state of control bits and flags.

See Also Saved Processor Status Register.

Debug With Arbitrary Record Format (DWARF)

ARM code generation tools generate debug information in DWARF2 format by default. From RVCT v2.2, you can optionally generate DWARF3 format (Draft Standard 9).

Debugger

An application that monitors and controls the execution of a second application. Usually used to find errors in the application program flow.

Deprecated

A deprecated option or feature is one that you are strongly discouraged from using. Deprecated options and features will not be supported in future versions of the product.

Doubleword

A 64-bit unit of information. Contents are taken as being an unsigned integer unless otherwise stated.

DWARF

See Debug With Arbitrary Record Format.

ELF

See Executable and Linking Format.

Executable and Linking Format (ELF)

The industry standard binary file format used by RealView Compilation Tools. ELF object format is produced by the ARM object producing tools such as armcc and armasm. The ARM linker accepts ELF object files and can output either an ELF executable file, or a partially linked ELF object.

Global variables

Variables that are accessible to all code in the application.

See Also Local variables.

Halfword

A 16-bit unit of information. Contents are taken as being an unsigned integer unless otherwise stated.

Hint

A hint instruction provides information to the hardware that the hardware can take advantage of. An implementation can choose whether to implement hint instructions or not. If they are not implemented, they execute as NOP.

Image

An executable file that has been loaded onto a processor for execution.

A binary execution file loaded onto a processor and given a thread of execution. An image can have multiple threads. An image is related to the processor on which its default thread runs.

Implementation defined

Means that the behavior is not architecturally defined, but must be defined and documented by individual implementations.

International Standards Organization (ISO)

An organization that specifies standards for, among other things, computer software. This supersedes the American National Standards Institute.

Interrupt

A change in the normal processing sequence of an application caused by, for example, an external signal.

Interworking

Producing an application that uses both ARM and Thumb code.

ISO

See International Standards Organization.

IT block

A block of up to four instructions following an If-Then (IT) instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others.

Jazelle

The Jazelle architecture extends the existing ARM architecture to enable direct execution of selected JVM (Java Virtual Machine) opcodes.

Library

A collection of assembler or compiler output objects grouped together into a single repository.

Linker

Software that produces a single image from one or more source assembler or compiler output objects.

Little-endian

Memory organization where the least significant byte of a word is at a lower address than the most significant byte.

Local variable

A variable that is only accessible to the subroutine that created it.

See Also Global variables.

Memory hint

A memory hint instruction enables you to provide advance information to memory systems about future memory accesses, without actually loading or storing any data.

MPCore

An integrated Symmetric Multiprocessor system (SMP) delivered as a traditional uniprocessor core. The chip contains up to four ARM1136J-S based CPUs with cache coherency.

PIC

Position Independent Code.

See Also ROPI.

PID

Position Independent Data.

See Also RWPI.

Procedure Call Standard for the ARM Architecture (AAPCS)

Procedure Call Standard for the ARM Architecture defines how registers and the stack will be used for subroutine calls.

Processor Status Register (PSR)

A register containing various control bits and flags.

See Also Current Processor Status Register, Saved Processor Status Register.

PSR

See Processor Status Register.

Read-Only Position Independent (ROPI)

Code and read-only data addresses can be changed at runtime.

Read Write Position Independent (RWPI)

Read/write data addresses can be changed at runtime.

RealView Compilation Tools (RVCT)

RealView Compilation Tools is a suite of tools, together with supporting documentation and examples, that enables you to write and build applications for the ARM family of RISC processors.

RealView Developer Suite (RVDS)

The latest suite of software development applications, together with supporting documentation and examples, that enable you to write and debug applications for the ARM family of RISC processors.

ROPI

See Read-Only Position Independent.

RVCT

See RealView Compilation Tools.

RVDS

See RealView Developer Suite.

RWPI

See Read Write Position Independent.

Saved Processor Status Register (SPSR)

SPSR. A register that holds a copy of what was in the Current Processor Status Register before the most recent exception. Each exception mode has its own SPSR.

Scope

The accessibility of a function or variable at a particular point in the application code. Symbols that have global scope are always accessible. Symbols with local or private scope are only accessible to code in the same subroutine or object.

Section

A block of software code or data for an Image.

Semihosting

A mechanism whereby the target communicates I/O requests made in the application code to the host system, rather attempting to support the I/O itself.

SIMD

See Single Instruction, Multiple Data.

Single Instruction, Multiple Data (SIMD)

Single Instruction, Multiple Data (SIMD) instructions perform similar operations on four 8-bit, or two 16-bit, data items held in 32-bit registers.

Software Interrupt (SWI)

An instruction that causes the processor to call a programmer-specified subroutine. Used by ARM to handle semihosting.

SPSR

See Saved Processor Status Register.

Stack

The portion of computer memory that is used to record the address of code that calls a subroutine. The stack can also be used for parameters and temporary variables.

SWI

See Software Interrupt.

Target

The actual target processor, (real or simulated), on which the target application is running.

The fundamental object in any debugging session. The basis of the debugging system. The environment in which the target software will run. It is essentially a collection of real or simulated processors.

Thumb instruction

One halfword or two halfwords that encode an operation for an ARM processor operating in Thumb state. Thumb instructions must be halfword-aligned.

Thumb state

A processor that is executing Thumb instructions is operating in Thumb state. The processor switches to ARM state (and to recognizing ARM instructions) when directed to do so by a state-changing instruction such as BX, BLX.

See Also ARM state.

TrustZone

ARM technology-optimized software that provides a secure execution environment to enable trusted programs and data to be separated from the operating system and applications.

Undefined

An attempt to execute an instruction that is not permitted causes an Undefined Instruction exception.

Unpredictable

The result of an instruction that cannot be relied upon. Unpredictable instructions or results must not represent security holes. Unpredictable instructions must not halt or hang the processor, or any parts of the system.

Vector Floating Point (VFP)

A standard for floating-point coprocessors where several data values can be processed by a single instruction.

Veneer

A small block of code used with subroutine calls when there is a requirement to change processor state or branch to an address that cannot be reached in the current processor state.

VFP

See Vector Floating Point.

Word

A 32-bit unit of information. Contents are taken as being an unsigned integer unless otherwise stated.

Zero initialized (ZI)

R/W memory used to hold variables that do not have an initial value. The memory is normally set to zero on reset.

ZI

See Zero Initialized.

Copyright © 2002-2005 ARM Limited. All rights reserved.ARM DUI 0204F
Non-Confidential