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Load a register with either:
a 32-bit constant value
an address.
This section describes the LDR pseudo-instruction
only. See Memory access instructions for information on the LDR instruction.
Also, see Loading with LDR Rd, =const,
for information on loading constants with the LDR pseudo-instruction.
LDR{cond}{.w}register,=[expr|label-expr]
where:
condis an optional condition code (see Conditional execution).
.Wis an optional instruction width specifier. See LDR in Thumb-2 for details.
registeris the register to be loaded.
exprevaluates to a numeric constant:
The assembler generates a MOV or MVN instruction,
if the value of is
within range.expr
If the value of is not within
range of a exprMOV or MVN instruction, the
assembler places the constant in a literal pool and generates a program-relative LDR instruction
that reads the constant from the literal pool.
label-expris a program-relative or external expression. The
assembler places the value of in
a literal pool and generates a program-relative label-exprLDR instruction
that loads the value from the literal pool.
If is
an external expression, or is not contained in the current section,
the assembler places a linker relocation directive in the object file.
The linker generates the address at link time.label-expr
If is
a local label (see Local labels),
the assembler places a linker relocation directive in the object
file and generates a symbol for that local label. The address is
generated at link time. If the local label references Thumb code,
the Thumb bit (bit 0) of the address is set.label-expr
In RVCT2.2, the Thumb bit of the address was not set. If you
have code that relies on this behavior, use the command line option --untyped_local_labels to
force the assembler not to set the Thumb bit when referencing labels
in Thumb code.
The main purposes of the LDR pseudo-instruction
are:
To generate literal constants
when an immediate value cannot be moved into a register because
it is out of range of the MOV and MVN instructions
To load a program-relative or external address into
a register. The address remains valid regardless of where the linker
places the ELF section containing the LDR.
An address loaded in this way is fixed at link time, so the code is not position-independent.
The offset from the PC to the value in the literal pool must be less than ±4KB (ARM, 32-bit Thumb-2) or in the range 0 to +1KB (Thumb, 16-bit Thumb-2). You are responsible for ensuring that there is a literal pool within range. See LTORG for more information.
See Loading constants into registers for
a more detailed explanation of how to use LDR, and
for more information on MOV and MVN.
This ARM pseudo-instruction is available in all versions of the ARM architecture.
For 32-bit Thumb-2, see LDR in Thumb-2.
This 16-bit Thumb pseudo-instruction is available in all T variants of the ARM architecture.
You can use the .W width specifier to force LDR to
generate a 32-bit instruction in Thumb-2 code.
LDR.W always generates a 32-bit instruction,
even if the constant could be loaded in a 16-bit MOV,
or there is a literal pool within reach of a 16-bit pc-relative
load.
LDR without .W always generates
a 16-bit instruction in Thumb code, even if that results in a 16-bit
pc-relative load for a constant that could be generated in a 32-bit MOV or MVN instruction.
LDR without .W never generates
a 16-bit flag-setting MOV instruction. Use the --diag_warning
1727 assembler command-line option to check when a 16-bit
instruction could have been used.
You can also use MOV32 (see MOV32 pseudo-instruction). This can place any
32-bit value in a register without a load operation, using two instructions.