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| Home > Assembler Reference > Command syntax > Splitting long LDMs and STMs |
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Use the following option to instruct the assembler to fault LDM and STM instructions
with large numbers of registers:
--split_ldm
This option faults LDM and STM instructions
if the maximum number of registers transferred exceeds:
five, for all STMs,
and for LDMs that do not load the PC
four, for LDMs that load the PC.
Avoiding large multiple register transfers can reduce interrupt latency on ARM systems that:
do not have a cache or a write buffer (for example, a cacheless ARM7TDMI)
use zero wait-state, 32-bit memory.
Also, avoiding large multiple register transfers:
always increases code size.
has no significant benefit for cached systems or processors with a write buffer.
has no benefit for systems without zero wait-state memory, or for systems with slow peripheral devices. Interrupt latency in such systems is determined by the number of cycles required for the slowest memory or peripheral access. This is typically much greater than the latency introduced by multiple register transfers.
| Copyright © 2002-2006 ARM Limited. All rights reserved. | ARM DUI 0204G |
| Non-Confidential | |
| PDF version | |
| Home > Assembler Reference > Command syntax > Splitting long LDMs and STMs |