RealView® Compilation Tools Assembler Guide 4.2.5. LDR and STR (post-indexed register offset)

4.2.5. LDR and STR (post-indexed register offset)

Load and Store. Byte and halfword loads are zero-extended or sign-extended to 32 bits.

Syntax

op{type}{T}{cond} Rd, {Rd2,} [Rn], +/-Rm {, shift}

where:

op

can be any one of:

LDR: Load Register
STR: Store Register.

type

can be any one of:

B: unsigned Byte
SB: Signed Byte (LDR only)
H: unsigned Halfword
SH: Signed Halfword (LDR only)
-: omitted, for Word
D: Doubleword.

cond

is an optional condition code (see Conditional execution).

T

is an optional suffix. If T is present, the memory system treats the access as though the processor was in User mode, even if it is in a privileged mode (see Processor mode). T has no effect in User mode.

Rd

is the ARM register to load or save.

Rd2

is the second ARM register to load or save (type == D only).

Rn

is the register on which the memory address is based. Rn must not be the same register as Rd or Rd2.

Rm

is a register containing a value to be used as the offset. Rm must not be r15.

shift

is an optional shift. See Operation and restrictions for details.

Operation and restrictions

The value in Rn is used as the memory address for the transfer. The offset is applied to the value in Rn after the data transfer takes place. In ARM, the offset can be added to or subtracted from Rn. In Thumb-2, the offset can only be added to Rn. The result is written back into Rn. Rn must not be r15.

The range of shifts allowed is:

Any one of the following for ARM Word and Unsigned Byte instructions:
- LSL 0 to 31
- LSR 1 to 32
- ASR 1 to 32
- ROR 1 to 31
- RRX
No shift is allowed for Thumb-2 instructions, or for ARM Signed Byte, unsigned Halfword, Signed halfword, or Doubleword instructions.

The T suffix is not available for Thumb-2 instructions, or for ARM doubleword instructions. It is available for all other ARM instructions.

Doubleword register restrictions

For Thumb-2 instructions, you must not specify r15 for either Rd or Rd2.

For ARM instructions:

Rd must be an even-numbered register
Rd must not be r14
Rd2 must be R(d + 1).

Thumb-2EE instructions

If the value in the base register is zero, execution branches to the NullCheck handler at HandlerBase - 4.

Loading to r15

Rd can be the PC, in either ARM or Thumb-2 code. In this case, type must be omitted.

A load to r15 (pc) causes a branch to the instruction at the address loaded.

In ARMv4, bits[1:0] of the value loaded must be zero.

In ARMv5 and above:

bits[1:0] of a value loaded to r15 must not have the value 0b10
if bit[0] of a value loaded to r15 is set, the processor changes to Thumb state.

You cannot use the T suffix when loading to r15.

Saving from r15

In Thumb code, you cannot save from r15.

In ARM code, avoid saving from r15 if possible.

If you do save from r15, the value saved is the address of the current instruction, plus an implementation-defined constant. The constant is always the same for a particular processor.

If your assembled code might be used on different processors, you can find out what the constant is at runtime using code like the following:

    SUB R1, PC, #4 ; R1 = address of following STR instruction
    STR PC, [R0]   ; Store address of STR instruction + offset,
    LDR R0, [R0]   ; then reload it
    SUB R0, R0, R1 ; Calculate the offset as the difference

If your code is to be assembled for a particular processor, the value of the constant is available in armasm as {PCSTOREOFFSET}.

Architectures

These ARM instructions are available in all versions of the ARM architecture.

These 32-bit Thumb-2 instructions are available in all T2 variants of the ARM architecture.

There are no 16-bit versions of these instructions.

In T and T2 variants of ARMv5 and above:

in ARM state, a load to r15 causes a change to Thumb state if bit[0] of the value loaded is 1
in Thumb state, a load to r15 causes a change to ARM state if bit[0] of the value loaded is 0.

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