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Store Return State.
SRS{addr_mode}{cond} {r13{!}}, #modenum
where:
addr_modeis any one of the following:
IAIncrement address After each transfer
IBIncrement address Before each transfer (ARM only)
DADecrement address After each transfer (ARM only)
DBDecrement address Before each transfer.
condis an optional condition code (see Conditional execution).
This is an unconditional instruction in ARM. is
only allowed in Thumb-2 code, using a preceding condIT instruction.
!is
an optional suffix. If ! is present, the
final address is written back into the r13 of the mode specified
by .modenum
modenumspecifies the number of the mode whose banked r13 is used as the base register, see Processor mode.
SRS stores the r14 and the SPSR of the current
mode, at the address contained in r13 of the mode specified by ,
and the following word respectively. Optionally updates r13 of the
mode specified by modenum.
This is compatible with the normal use of the modenumSTM instruction
for stack accesses, see LDM and STM.
You can use SRS to store return state for an
exception handler on a different stack from the one automatically
selected.
In Thumb-2EE, if the value in the base register is zero, execution branches to the NullCheck handler at HandlerBase - 4.
Where addresses are not word-aligned, SRS ignores
the least significant two bits of the specified address.
The time order of the accesses to individual words of memory
generated by SRS is not architecturally defined. Do
not use this instruction on memory-mapped I/O locations where access
order matters.
SRS is unpredictable in User and System modes (that
is, it cannot be relied upon), because they do not have SPSRs.
This ARM instruction is available in ARMv6 and above.
This 32-bit Thumb-2 instruction is available in T2 variants of ARMv6 and above.
There is no 16-bit version of this instruction.