RealView ® CompilationTools Assembler Guide

Version 3.0


Table of Contents

Preface
About this book
Intended audience
Using this book
Typographical conventions
Further reading
Feedback
Feedback on RealView Compilation Tools
Feedback on this book
1. Introduction
1.1. About the RealView Compilation Tools assemblers
1.1.1. ARM assembly language
1.1.2. Wireless MMX Technology instructions
1.1.3. NEON technology
1.1.4. Using the examples
2. Writing ARM Assembly Language
2.1. Introduction
2.1.1. Code examples
2.2. Overview of the ARM architecture
2.2.1. Architecture versions
2.2.2. ARM, Thumb, Thumb-2, and Thumb-2EE instructionsets
2.2.3. ARM, Thumb, andThumbEE state
2.2.4. Processor mode
2.2.5. Registers
2.2.6. Instruction setoverview
2.2.7. Instruction capabilities
2.3. Structure of assembly language modules
2.3.1. Layout of assembly language sourcefiles
2.3.2. An example ARM assemblylanguage module
2.3.3. Calling subroutines
2.4. Conditional execution
2.4.1. The ALU status flags
2.4.2. Conditional execution
2.4.3. Using conditionalexecution
2.4.4. Example of the useof conditional execution
2.4.5. The Q flag
2.5. Loading constants into registers
2.5.1. Direct loading withMOV and MVN
2.5.2. Loading with MOV32
2.5.3. Loading with LDR Rd, =const
2.5.4. Loading floating-point constants
2.6. Loading addresses into registers
2.6.1. Direct loading with ADR and ADRL
2.6.2. Loading addresses withLDR Rd, =label
2.7. Load and store multiple register instructions
2.7.1. Load and store multipleinstructions available in ARM and Thumb
2.7.2. Implementing stackswith LDM and STM
2.7.3. Block copy with LDMand STM
2.8. Using macros
2.8.1. Test-and-branch macro example
2.8.2. Unsigned integer division macro example
2.9. Adding symbol versions
2.10. Using frame directives
2.11. Assembly language changes
3. Assembler Reference
3.1. Command syntax
3.1.1. Obtaining a list of available options
3.1.2. Specifying command-line options with an environmentvariable
3.1.3. AAPCS
3.1.4. Floating-point model
3.1.5. CPU names
3.1.6. FPU names
3.1.7. Memory access attributes
3.1.8. Pre-executing aSET directive
3.1.9. Splitting long LDMs and STMs
3.1.10. Listing output to a file
3.1.11. Controlling the output of diagnosticmessages
3.1.12. Controlling exceptiontable generation
3.2. Format of source lines
3.3. Predefined register and coprocessornames
3.3.1. Predeclared register names
3.3.2. Predeclared program status register names
3.3.3. Predeclared floating-point register names
3.3.4. Predeclared NEON register names
3.3.5. Predeclared coprocessor names
3.4. Built-in variables and constants
3.5. Symbols
3.5.1. Symbol naming rules
3.5.2. Variables
3.5.3. Numeric constants
3.5.4. Assembly time substitutionof variables
3.5.5. Labels
3.5.6. Local labels
3.6. Expressions, literals, and operators
3.6.1. String expressions
3.6.2. String literals
3.6.3. Numeric expressions
3.6.4. Numeric literals
3.6.5. Floating-point literals
3.6.6. Register-relative andprogram-relative expressions
3.6.7. Logical expressions
3.6.8. Logical literals
3.6.9. Operator precedence
3.6.10. Unary operators
3.6.11. Binary operators
3.7. Diagnostic messages
3.7.1. Interlocks
3.8. Using the C preprocessor
4. ARM and Thumb Instructions
4.1. Instruction summary
4.2. Memory access instructions
4.2.1. Address alignment
4.2.2. LDR and STR (zero,immediate, or pre-indexed immediate offset)
4.2.3. LDR and STR (post-indexedimmediate offset)
4.2.4. LDR and STR (registeror pre-indexed register offset)
4.2.5. LDR and STR (post-indexedregister offset)
4.2.6. LDR (PC-relative)
4.2.7. ADR
4.2.8. PLD and PLI
4.2.9. LDM and STM
4.2.10. PUSH and POP
4.2.11. RFE
4.2.12. SRS
4.2.13. LDREX and STREX
4.2.14. CLREX
4.2.15. SWP and SWPB
4.3. General data processing instructions
4.3.1. Flexible second operand
4.3.2. ADD, SUB, RSB, ADC,SBC, and RSC
4.3.3. SUBS PC, LR (Thumb-2only)
4.3.4. AND, ORR, EOR, BIC,and ORN
4.3.5. CLZ
4.3.6. CMP and CMN
4.3.7. MOV and MVN
4.3.8. MOVT
4.3.9. TST and TEQ
4.3.10. SEL
4.3.11. REV, REV16, REVSH,and RBIT
4.3.12. ASR, LSL, LSR, ROR,and RRX
4.3.13. IT
4.3.14. SDIV and UDIV
4.4. Multiply instructions
4.4.1. MUL, MLA, and MLS
4.4.2. UMULL, UMLAL, SMULL,and SMLAL
4.4.3. SMULxy andSMLAxy
4.4.4. SMULWy andSMLAWy
4.4.5. SMLALxy
4.4.6. SMUAD{X} and SMUSD{X}
4.4.7. SMMUL, SMMLA, and SMMLS
4.4.8. SMLAD and SMLSD
4.4.9. SMLALD and SMLSLD
4.4.10. UMAAL
4.4.11. MIA, MIAPH, and MIAxy
4.5. Saturating instructions
4.5.1. What are saturating instructions?
4.5.2. QADD, QSUB, QDADD,and QDSUB
4.5.3. SSAT and USAT
4.6. Parallel instructions
4.6.1. Parallel add and subtract
4.6.2. USAD8 and USADA8
4.6.3. SSAT16 and USAT16
4.7. Packing and unpacking instructions
4.7.1. BFC and BFI
4.7.2. SBFX and UBFX
4.7.3. SXT, SXTA, UXT, andUXTA
4.7.4. PKHBT and PKHTB
4.8. Branch instructions
4.8.1. B, BL, BX, BLX, andBXJ
4.8.2. CBZ and CBNZ
4.8.3. TBB and TBH
4.9. Coprocessor instructions
4.9.1. CDP and CDP2
4.9.2. MCR, MCR2, MCRR, andMCRR2
4.9.3. MRC, MRC2, MRRC andMRRC2
4.9.4. LDC and STC
4.9.5. LDC2 and STC2
4.10. Miscellaneous instructions
4.10.1. BKPT
4.10.2. SVC
4.10.3. MRS
4.10.4. MSR
4.10.5. CPS
4.10.6. SMC
4.10.7. SETEND
4.10.8. NOP, SEV, WFE, WFI,and YIELD
4.10.9. DBG, DMB, DSB, andISB
4.10.10. MAR and MRA
4.10.11. ENTERX and LEAVEX
4.10.12. CHKA
4.10.13. HB, HBL, HBLP, andHBP
4.11. Pseudo-instructions
4.11.1. ADRL pseudo-instruction
4.11.2. MOV32 pseudo-instruction
4.11.3. LDR pseudo-instruction
5. NEON and VFP Programming
5.1. The NEON / VFP register bank
5.1.1. NEON views of the register bank
5.1.2. VFPv3 views of the register bank
5.2. Condition codes
5.3. General information
5.3.1. Exceptions
5.3.2. Architecture versions
5.3.3. NEON data types
5.3.4. Normal, Long, Wide,Narrow, and saturating instructions in NEON
5.3.5. NEON Scalars
5.3.6. Polynomial arithmetic over {0,1}
5.4. Instructions shared by NEON and VFP
5.4.1. VLDR and VSTR
5.4.2. VLDM and VSTM
5.4.3. VMOV (between two ARMregisters and NEON / VFP)
5.4.4. VMOV (between one ARMregister and NEON / VFP)
5.4.5. VMOV (between one ARMregister and single precision VFP)
5.4.6. MRS and MSR
5.5. NEON logical and compare operations
5.5.1. VAND, VBIC, VEOR, VORN,and VORR (register)
5.5.2. VBIC and VORR (immediate)
5.5.3. VBIF, VBIT, and VBSL
5.5.4. VNOT
5.5.5. VACGE and VACGT
5.5.6. VCEQ, VCGE, VCGT, VCLE,and VCLT
5.5.7. VTST
5.6. NEON general data processing instructions
5.6.1. VCVT
5.6.2. VDUP
5.6.3. VEXT
5.6.4. VMOV, VMVN (immediate)
5.6.5. VMOV (register)
5.6.6. VMOVL, V{Q}MOVN, VQMOVUN
5.6.7. VREV
5.6.8. VSWP
5.6.9. VTBL, VTBX
5.6.10. VTRN
5.6.11. VUZP, VZIP
5.7. NEON shift instructions
5.7.1. VSHL, VQSHL, VQSHLU,and VSHLL (by immediate)
5.7.2. V{Q}{R}SHL (by signedvariable)
5.7.3. V{R}SHR{N}, V{R}SRA(by immediate)
5.7.4. VQ{R}SHR{U}N (by immediate)
5.7.5. VSLI and VSRI
5.8. NEON general arithmetic instructions
5.8.1. VABA{L} and VABD{L}
5.8.2. V{Q}ABS and V{Q}NEG
5.8.3. V{Q}ADD, VADDL, VADDW,V{Q}SUB, VSUBL, and VSUBW
5.8.4. V{R}ADDHN and V{R}SUBHN
5.8.5. V{R}HADD and VHSUB
5.8.6. VPADD{L}, VPADAL
5.8.7. VMAX, VMIN, VPMAX,and VPMIN
5.8.8. VCLS, VCLZ, and VCNT
5.8.9. VRECPE and VRSQRTE
5.8.10. VRECPS and VRSQRTS
5.9. NEON multiply instructions
5.9.1. VMUL{L}, VMLA{L}, andVMLS{L}
5.9.2. VMUL{L}, VMLA{L}, andVMLS{L} (by scalar)
5.9.3. VQDMULL, VQDMLAL, andVQDMLSL (by vector or by scalar)
5.9.4. VQ{R}DMULH (by vectoror by scalar)
5.10. NEON load / store element and structure instructions
5.10.1. Interleaving
5.10.2. Alignment restrictionsin load / store element and structure instructions
5.10.3. VLDn andVSTn (single n -elementstructure to one lane)
5.10.4. VLDn (single n -elementstructure to all lanes)
5.10.5. VLDn andVSTn (multiple n -elementstructures)
5.11. NEON pseudo-instructions
5.11.1. VAND and VORN (immediate)
5.11.2. VACLE and VACLT
5.11.3. VCLE and VCLT
5.12. The Vector Floating Point coprocessor
5.13. VFP registers
5.13.1. Register banks
5.13.2. Vectors
5.14. VFP vector and scalar operations
5.14.1. Control of scalar, vector, and mixedoperations
5.15. VFP / NEON system registers
5.15.1. FPSCR, the floating-point status andcontrol register
5.15.2. FPEXC, the floating-pointexception register
5.15.3. FPSID, the floating-point system IDregister
5.15.4. Modifying individualbits of a NEON / VFP system register
5.16. Flush-to-zero mode
5.16.1. When to use flush-to-zero mode
5.16.2. The effects of using flush-to-zero mode
5.16.3. Operations not affected by flush-to-zeromode
5.17. VFP instructions
5.17.1. FABS, FCPY, and FNEG
5.17.2. FADD and FSUB
5.17.3. FCMP
5.17.4. FCVTDS
5.17.5. FCVTSD
5.17.6. FDIV
5.17.7. FMAC, FNMAC, FMSC,and FNMSC
5.17.8. FMUL and FNMUL
5.17.9. FSITO and FUITO
5.17.10. FSQRT
5.17.11. FTOSI and FTOUI
5.17.12. FCONSTS and FCONSTD
5.17.13. FSHTOS, FSHTOD, FSLTOS,FSLTOD, FUHTOS, FUHTOD, FULTOS, and FULTOD
5.17.14. FTOSHS, FTOSHD, FTOSLS,FTOSLD, FTOUHS, FTOUHD, FTOULS, and FTOULD
5.18. VFP pseudo-instruction
5.18.1. VLDR pseudo-instruction
5.19. VFP directives andvector notation
5.19.1. Vector notation
5.19.2. VFPASSERT SCALAR
5.19.3. VFPASSERT VECTOR
6. Wireless MMX Technology Instructions
6.1. Introduction
6.2. ARM support for Wireless MMX Technology
6.2.1. Registers
6.2.2. Directives, WRN and WCN
6.2.3. Frame directives
6.2.4. Load and store instructions
6.2.5. Wireless MMX Technology and XScaleinstructions
6.3. Instruction summary
6.3.1. Pseudo-instructions
7. Directives Reference
7.1. Alphabetical list of directives
7.2. Symbol definition directives
7.2.1. GBLA, GBLL, and GBLS
7.2.2. LCLA, LCLL, and LCLS
7.2.3. SETA, SETL, and SETS
7.2.4. RELOC
7.2.5. RN
7.2.6. RLIST
7.2.7. CN
7.2.8. CP
7.2.9. DN and SN
7.2.10. QN
7.3. Data definition directives
7.3.1. LTORG
7.3.2. MAP
7.3.3. FIELD
7.3.4. SPACE
7.3.5. DCB
7.3.6. DCD and DCDU
7.3.7. DCDO
7.3.8. DCFD and DCFDU
7.3.9. DCFS and DCFSU
7.3.10. DCI
7.3.11. DCQ and DCQU
7.3.12. DCW and DCWU
7.3.13. COMMON
7.3.14. DATA
7.4. Assembly control directives
7.4.1. Nesting directives
7.4.2. MACRO and MEND
7.4.3. MEXIT
7.4.4. IF, ELSE, ENDIF, andELIF
7.4.5. WHILE and WEND
7.5. Frame directives
7.5.1. FRAME ADDRESS
7.5.2. FRAME POP
7.5.3. FRAME PUSH
7.5.4. FRAME REGISTER
7.5.5. FRAME RESTORE
7.5.6. FRAME RETURN ADDRESS
7.5.7. FRAME SAVE
7.5.8. FRAME STATE REMEMBER
7.5.9. FRAME STATE RESTORE
7.5.10. FRAME UNWIND ON
7.5.11. FRAME UNWIND OFF
7.5.12. FUNCTION or PROC
7.5.13. ENDFUNC or ENDP
7.6. Reporting directives
7.6.1. ASSERT
7.6.2. INFO
7.6.3. OPT
7.6.4. TTL and SUBT
7.7. Instruction set and syntax selectiondirectives
7.7.1. ARM, THUMB, THUMBX,CODE16 and CODE32
7.8. Miscellaneous directives
7.8.1. ALIGN
7.8.2. AREA
7.8.3. END
7.8.4. ENTRY
7.8.5. EQU
7.8.6. EXPORT or GLOBAL
7.8.7. EXPORTAS
7.8.8. EXTERN
7.8.9. GET or INCLUDE
7.8.10. IMPORT
7.8.11. INCBIN
7.8.12. KEEP
7.8.13. NOFP
7.8.14. REQUIRE
7.8.15. REQUIRE8 and PRESERVE8
7.8.16. ROUT

List of Tables

2.1. ARM processor modes
2.2. Condition code suffixes
2.3. Conditional branches only
2.4. All instructions conditional
2.5. ARM state immediate constants (8-bit)
2.6. ARM state immediate constants in MOV instructions
2.7. Thumb state immediate constants
2.8. Thumb state immediate constants in MOV instructions
2.9. Suffixes for load and store multiple instructions
2.10. Changes from earlier ARM assembly language
2.11. Relaxation of requirements
2.12. Differences between old Thumb syntax and new syntax
3.1. Severity of diagnostic messages
3.2. Built-in variables
3.3. Built-in Boolean constants
3.4. Operator precedence in armasm
3.5. Operator precedence in C
3.6. Unary operators that return strings
3.7. Unary operators that return numeric or logical values
3.8. Multiplicative operators
3.9. String manipulation operators
3.10. Shift operators
3.11. Addition, subtraction, and logical operators
3.12. Relational operators
3.13. Boolean operators
4.1. Location of instructions
4.2. Branch instruction availability and range
5.1. Location of NEON instructions
5.2. Location of shared NEON / VFP instructions
5.3. Location of VFP instructions
5.4. Condition codes
5.5. NEON saturation ranges
5.6. Available constants
5.7. Results for out-of-range inputs
5.8. Results for out-of-range inputs
5.9. Permitted combinations of parameters
5.10. Permitted combinations of parameters
5.11. Permitted combinations of parameters
6.1. Status and Control registers
6.2. Wireless MMX Technology instructions
6.3. Wireless MMX Technology pseudo-instructions
7.1. Location of directives
7.2. OPT directive settings

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Revision History
Revision A August2002 Release 1.2
Revision B January2003 Release 2.0
Revision C September2003 Release 2.0.1 for RVDS v2.0
Revision D January2004 Release 2.1 for RVDS v2.1
Revision E December2004 Release 2.2 for RVDS v2.2
Revision F May2005 Release 2.2 for RVDS v2.2 SP1
Revision G March 2006 Release3.0 for RVDS v3.0
Copyright © 2002-2006 ARM Limited. All rights reserved. ARM DUI 0204G
Non-Confidential