4.3.4. LDR and STR (User mode)

Load and Store, byte, halfword, or word, with User mode privilege.

When these instructions are executed in a privileged mode, they access memory with the same restrictions as they would have if they were executed in User mode.

In User mode, these instructions behave in exactly the same way as normal memory accesses.

Syntax

op{type}T{cond} Rt, [Rn {, #offset}]       ; immediate offset (Thumb-2 only)
op{type}T{cond} Rt, [Rn] {, #offset}       ; post-indexed (ARM only)
op{type}T{cond} Rt, [Rn], +/-Rm {, shift}  ; post-indexed (register) (ARM only)

where:

op

can be either:

LDR

Load Register

STR

Store Register.

type

can be any one of:

B

unsigned Byte (Zero extend to 32 bits on loads.)

SB

Signed Byte (LDR only. Sign extend to 32 bits.)

H

unsigned Halfword (Zero extend to 32 bits on loads.)

SH

Signed Halfword (LDR only. Sign extend to 32 bits.)

-

omitted, for Word.

cond

is an optional condition code (see Conditional execution).

Rt

is the register to load or store.

Rn

is the register on which the memory address is based.

offset

is an offset. If offset is omitted, the address is the value in Rn.

Rm

is a register containing a value to be used as the offset. Rm must not be r15.

shift

is an optional shift.

Offset ranges and architectures

Table 4.2 shows the ranges of offsets and availability of these instructions.

Table 4.4. Offsets and architectures, LDR/STR (User mode)

InstructionImmediate offsetPost-indexed+/-Rm [a]shiftArch.
ARM, word or byteNot available-4095 to 4095+/-RmLSL #0-31All
    LSR #1-32 
    ASR #1-32 
    ROR #1-31 
    RRX 
ARM, signed byte, halfword, or signed halfwordNot available-255 to 255+/-RmNot availableAll
32-bit Thumb, word, halfword, signed halfword, byte, or signed byte0 to 255Not availableNot availablev6T2, v7

[a] You can use -Rm, +Rm, or Rm.


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