RealView Compilation Tools Assembler Guide: 4.3.5. LDR (pc‑relative)

4.3.5. LDR (pc-relative)

Load register. The address is an offset from the pc.

Note

Syntax

LDR{type}{cond}{.W} Rt, label

LDRD{cond} Rt, Rt2, label        ; Doubleword

where:

type

can be any one of:

B: unsigned Byte (Zero extend to 32 bits on loads.)
SB: Signed Byte (LDR only. Sign extend to 32 bits.)
H: unsigned Halfword (Zero extend to 32 bits on loads.)
SH: Signed Halfword (LDR only. Sign extend to 32 bits.)
-: omitted, for Word.

cond

is an optional condition code (see Conditional execution).

.W

is an optional instruction width specifier. See LDR (pc‑relative) in Thumb‑2 for details.

Rt

is the register to load or store.

Rt2

is the second register to load or store.

label

is a program-relative expression. See Register‑relative and program‑relative expressions for more information.

label must be within a limited distance of the current instruction. See Offset range and architectures for details.

Offset range and architectures

The assembler calculates the offset from the pc for you. The assembler generates an error if label is out of range.

Table 4.5 shows the possible offsets between label and the current instruction.

Table 4.5. pc-relative offsets

Instruction	Offset range	Architectures
ARM `LDR`, `LDRB`, `LDRSB`, `LDRH`, `LDRSH` ^[a]	+/- 4095	All
ARM `LDRD`	+/- 255	v5TE +
32-bit Thumb `LDR`, `LDRB`, `LDRSB`, `LDRH`, `LDRSH` ^[a]	+/- 4095	v6T2, v7
32-bit Thumb `LDRD`	+/- 1020 ^[b]	v6T2, v7
16-bit Thumb `LDR` ^[c]	0-1020 ^[b]	All T
^[a]For word loads, Rt can be the pc. A load to the pc causes a branch to the address loaded. In ARMv4, bits[1:0] of the address loaded must be 0b00. In ARMv5 and above, bits[1:0] must not be 0b10, and if bit[0] is 1, execution continues in Thumb state, otherwise execution continues in ARM state. ^[b]Must be a multiple of 4. ^[c]Rt must be in the range r0-r7. There are no byte, halfword, or doubleword 16-bit instructions.

LDR (pc-relative) in Thumb-2

You can use the .W width specifier to force LDR to generate a 32-bit instruction in Thumb-2 code. LDR.W always generates a 32-bit instruction, even if the target could be reached using a 16-bit LDR.

For forward references, LDR without .W always generates a 16-bit instruction in Thumb code, even if that results in failure for a target that could be reached using a 32-bit Thumb-2 LDR instruction.

Doubleword register restrictions

For Thumb-2 instructions, you must not specify sp or pc for either Rt or Rt2.

For ARM instructions:

Rt must be an even-numbered register
Rt must not be lr
it is strongly recommended that you do not use r12 for Rt
Rt2 must be R(t + 1).

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