4.11.8. NOP, SEV, WFE, WFI, and YIELD

No Operation, Set Event, Wait For Event, Wait for Interrupt, and Yield.

Syntax

NOP{cond}
SEV{cond}
WFE{cond}
WFI{cond}
YIELD{cond}

where:

cond

is an optional condition code (see Conditional execution).

Usage

These are hint instructions. It is optional whether they are implemented or not. If any one of them is not implemented, it behaves as a NOP.

NOP

NOP does nothing. If NOP is not implemented as a specific instruction on your target architecture, the assembler generates an alternative instruction that does nothing, such as MOV r0, r0 (ARM) or MOV r8, r8 (Thumb).

NOP is not necessarily a time-consuming NOP. The processor might remove it from the pipeline before it reaches the execution stage.

You can use NOP for padding, for example to place the following instruction on a 64-bit boundary.

SEV

SEV causes an event to be signaled to all cores within a multiprocessor system. If SEV is implemented, WFE must also be implemented.

WFE

If the Event Register is not set, WFE suspends execution until one of the following events occurs:

  • an IRQ interrupt, unless masked by the CPSR I-bit

  • an FIQ interrupt, unless masked by the CPSR F-bit

  • an Imprecise Data abort, unless masked by the CPSR A-bit

  • a Debug Entry request, if Debug is enabled

  • an Event signaled by another processor using the SEV instruction.

If the Event Register is set, WFE clears it and returns immediately.

If WFE is implemented, SEV must also be implemented.

WFI

WFI suspends execution until one of the following events occurs:

  • an IRQ interrupt, regardless of the CPSR I-bit

  • an FIQ interrupt, regardless of the CPSR F-bit

  • an Imprecise Data abort, unless masked by the CPSR A-bit

  • a Debug Entry request, regardless of whether Debug is enabled.

YIELD

YIELD indicates to the hardware that the current thread is performing a task, for example a spinlock, that can be swapped out. Hardware can use this hint to suspend and resume threads in a multithreading system.

Architectures

These ARM instructions are available in ARMv6T2 and ARMv7.

These 32-bit Thumb instructions are available in ARMv6T2 and ARMv7.

These 16-bit Thumb instructions are available in ARMv6T2 and above, and K variants of ARMv6.

NOP is available on all other ARM and Thumb architectures as a pseudo-instruction.

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