5.6.1. VLDR and VSTR

Extension register load and store.


VLDR{cond}{.size} Fd, [Rn{, #offset}]
VSTR{cond}{.size} Fd, [Rn{, #offset}]
VLDR{cond}{.size} Fd, label
VSTR{cond}{.size} Fd, label



is an optional condition code (see Condition codes).


is an optional data size specifier. Must be 32 if Fd is a single precision VFP register, or 64 otherwise.


is the extension register to be loaded or saved. For a NEON instruction, it must be a D register. For a VFP instruction, it can be either a D or S register.


is the ARM register holding the base address for the transfer.


is an optional numeric expression. It must evaluate to a numeric constant at assembly time. The value must be a multiple of 4, and lie in the range -1020 to +1020. The value is added to the base address to form the address used for the transfer.


is a program-relative expression. See Register‑relative and program‑relative expressions for more information.

label must be within ±1KB of the current instruction.


The VLDR instruction loads an extension register from memory. The VSTR instruction saves the contents of an extension register to memory.

One word is transferred if Fd is a single precision register (VFP only). Two words are transferred otherwise.

There is also an VLDR pseudo-instruction (see VLDR pseudo‑instruction).

Copyright © 2002-2010 ARM. All rights reserved.ARM DUI 0204J