5.6.2. VLDM, VSTM, VPOP, and VPUSH

Extension register load multiple, store multiple, pop from stack, push onto stack.


VLDMmode{cond} Rn{!}, Registers
VSTMmode{cond} Rn{!}, Registers
VPOP{cond} Registers
VPUSH{cond} Registers



must be one of:


meaning Increment address After each transfer. IA is the default, and can be omitted.


meaning Decrement address Before each transfer.


meaning Empty Ascending stack operation. This is the same as DB for loads, and the same as IA for saves.


meaning Full Descending stack operation. This is the same as IA for loads, and the same as DB for saves.

See Table 2.9 for equivalent addressing mode suffixes.


is an optional condition code (see Condition codes).


is the ARM register holding the base address for the transfer.


is optional. ! specifies that the updated base address must be written back to Rn. If ! is not specified, mode must be IA.


is a list of consecutive extension registers enclosed in braces, { and }. The list can be comma-separated, or in range format. There must be at least one register in the list.

You can specify S, D, or Q registers, but they must not be mixed. The number of registers must not exceed 16 D registers, or 8 Q registers. If Q registers are specified, on disassembly they are shown as D registers.


VPOP Registers is equivalent to VLDM sp!, Registers.

VPUSH Registers is equivalent to VSTMDB sp!, Registers.

You can use either form of these instructions. They disassemble to VPOP and VPUSH.

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