2.4.2. Conditional execution

The instructions that can be conditional have an optional condition code, shown in syntax descriptions as {cond}. This condition is encoded in ARM instructions, and encoded in a preceding IT instruction for Thumb-2 instructions. An instruction with a condition code is only executed if the condition code flags in the APSR meet the specified condition. Table 2.2 shows the condition codes that you can use.

In Thumb state on pre-Thumb-2 processors, the {cond} field is only permitted on certain branch instructions.

Table 2.2 also shows the relationship between condition code suffixes and the N, Z, C and V flags.

Table 2.2. Condition code suffixes

EQZ setEqual
NEZ clearNot equal
CS or HSC setHigher or same (unsigned >= )
CC or LOC clearLower (unsigned < )
MIN setNegative
PLN clearPositive or zero
VSV setOverflow
VCV clearNo overflow
HIC set and Z clearHigher (unsigned >)
LSC clear or Z setLower or same (unsigned <=)
GEN and V the sameSigned >=
LTN and V differSigned <
GTZ clear, N and V the sameSigned >
LEZ set, N and V differSigned <=
ALAnyAlways. This suffix is normally omitted.

Example 2.3 shows an example of conditional execution.

Example 2.3. 

    ADD     r0, r1, r2    ; r0 = r1 + r2, don't update flags
    ADDS    r0, r1, r2    ; r0 = r1 + r2, and update flags
    ADDSCS  r0, r1, r2    ; If C flag set then r0 = r1 + r2, and update flags
    CMP     r0, r1        ; update flags based on r0-r1.

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