2.2.5. Registers

ARM processors have 37 registers. The registers are arranged in partially overlapping banks. There is a different register bank for each processor mode. The banked registers give rapid context switching for dealing with processor exceptions and privileged operations. See ARM Architecture Reference Manual for a detailed description of how registers are banked.

The following registers are available:

Thirty general-purpose, 32-bit registers

Fifteen general-purpose registers are visible at any one time, depending on the current processor mode. These are r0-r12, sp, lr.

sp (or r13) is the stack pointer. The C and C++ compilers always use sp as the stack pointer. In Thumb-2, sp is strictly defined as the stack pointer, so many instructions that are not useful for stack manipulation are unpredictable if they use sp. Use of sp as a general purpose register is discouraged.

In User mode, lr (or r14) is used as a link register to store the return address when a subroutine call is made. It can also be used as a general-purpose register if the return address is stored on the stack.

In the exception handling modes, lr holds the return address for the exception, or a subroutine return address if subroutine calls are executed within an exception. lr can be used as a general-purpose register if the return address is stored on the stack.

The Program Counter (PC)

The Program Counter is accessed as pc (or r15). It is incremented by one word (four bytes) for each instruction in ARM state, or by the size of the instruction executed in Thumb state. Branch instructions load the destination address into pc. You can also load the PC directly using data operation instructions. For example, to return from a subroutine, you can copy the link register into the PC using:

    MOV pc,lr

During execution, pc does not contain the address of the currently executing instruction. The address of the currently executing instruction is typically pc-8 for ARM, or pc-4 for Thumb.

The Application Program Status Register (APSR)

The APSR holds copies of the Arithmetic Logic Unit (ALU) status flags. They are used to determine whether conditional instructions are executed or not. See Conditional execution for more information.

On ARMv5TE, and ARMv6 and above, the APSR also holds the Q flag (see The ALU status flags).

On ARMv6 and above, the APSR also holds the GE flags (see Parallel add and subtract).

These flags are accessible in all modes, using MSR and MRS instructions. See MRS and MSR for details.

The Current Program Status Register (CPSR)

The CPSR holds:

  • the APSR flags

  • the current processor mode

  • interrupt disable flags

  • current processor state (ARM, Thumb, ThumbEE, or Jazelle)

  • execution state bits for the IT block.

The execution state bits control conditional execution in the IT block (see IT) and are only available on ARMv6T2 and above.

Only the APSR flags are accessible in all modes. The remaining bits of the CPSR are accessible only in privileged modes, using MSR and MRS instructions. See MRS and MSR for details.

Saved Program Status Registers (SPSRs)

The SPSRs are used to store the CPSR when an exception is taken. One SPSR is accessible in each of the exception-handling modes. User mode and System mode do not have an SPSR because they are not exception handling modes. See Chapter 6 Handling Processor Exceptions in the Developer Guide for more information.

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