RealView Compilation Tools Assembler Guide: 5.12.4. VLDn (single n‑element structure to all lanes)

5.12.4. VLD`n` (single `n`-element structure to all lanes)

Vector Load single n-element structure to all lanes. It loads multiple copies of one n-element structure from memory into one or more NEON registers.

Syntax

VLDn{cond}.datatype list, [Rn{@align}]{!}

VLDn{cond}.datatype list, [Rn{@align}], Rm

where:

n: must be one of 1, 2, 3, or 4.
cond: is an optional condition code (see Condition codes).
datatype: see Table 5.13 .
list: specifies the NEON register list. See Table 5.13 for options.
Rn: is the ARM register containing the base address. Rn cannot be r15.
align: specifies an optional alignment. See Table 5.13 for options.
!: if ! is present, Rn is updated to (Rn + the number of bytes transferred by the instruction). The update occurs after all the loads or stores have taken place.
Rm: is an ARM register containing an offset from the base address. If Rm is present, Rn is updated to (Rn + Rm) after the address is used to access memory. Rm cannot be r13 or r15.

Table 5.13. Permitted combinations of parameters

`n`	`datatype`	list ^[a]	`align` ^[b]	alignment
1	`8`	`{Dd[]}`	-	Standard only
		`{Dd[],D(d+1)[]}`	-	Standard only
	`16`	`{Dd[]}`	`@16`	2-byte
		`{Dd[],D(d+1)[]}`	`@16`	2-byte
	`32`	`{Dd[]}`	`@32`	4-byte
		`{Dd[],D(d+1)[]}`	`@32`	4-byte
2	`8`	`{Dd[], D(d+1)[]}`	`@8`	byte
		`{Dd[], D(d+2)[]}`	`@8`	byte
	`16`	`{Dd[], D(d+1)[]}`	`@16`	2-byte
		`{Dd[], D(d+2)[]}`	`@16`	2-byte
	`32`	`{Dd[], D(d+1)[]}`	`@32`	4-byte
		`{Dd[], D(d+2)[]}`	`@32`	4-byte
3	`8`, `16`, or `32`	`{Dd[], D(d+1)[], D(d+2)[]}`	-	Standard only
		`{Dd[], D(d+2)[], D(d+4)[]}`	-	Standard only
4	`8`	`{Dd[], D(d+1)[], D(d+2)[], D(d+3)[]}`	`@32`	4-byte
		`{Dd[], D(d+2)[], D(d+4)[], D(d+6)[]}`	`@32`	4-byte
	16	`{Dd[], D(d+1)[], D(d+2)[], D(d+3)[]}`	`@64`	8-byte
		`{Dd[], D(d+2)[], D(d+4)[], D(d+6)[]}`	`@64`	8-byte
	32	`{Dd[], D(d+1)[], D(d+2)[], D(d+3)[]}`	`@64` or `@128`	8-byte or 16-byte
		`{Dd[], D(d+2)[], D(d+4)[], D(d+6)[]}`	`@64` or `@128`	8-byte or 16-byte
^[a]Every register in the list must be in the range D0-D31. ^[b]`Align` can be omitted. In this case, standard alignment rules apply, see Alignment restrictions in load and store, element and structure instructions.

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5.12.4. VLDn (single n-element structure to all lanes)

Syntax

5.12.4. VLD`n` (single `n`-element structure to all lanes)