5.12.4. VLDn (single n-element structure to all lanes)

Vector Load single n-element structure to all lanes. It loads multiple copies of one n-element structure from memory into one or more NEON registers.


VLDn{cond}.datatype list, [Rn{@align}]{!}
VLDn{cond}.datatype list, [Rn{@align}], Rm



must be one of 1, 2, 3, or 4.


is an optional condition code (see Condition codes).


specifies the NEON register list. See Table 5.13 for options.


is the ARM register containing the base address. Rn cannot be r15.


specifies an optional alignment. See Table 5.13 for options.


if ! is present, Rn is updated to (Rn + the number of bytes transferred by the instruction). The update occurs after all the loads or stores have taken place.


is an ARM register containing an offset from the base address. If Rm is present, Rn is updated to (Rn + Rm) after the address is used to access memory. Rm cannot be r13 or r15.

Table 5.13. Permitted combinations of parameters

ndatatypelist [a]align [b]alignment
18{Dd[]}-Standard only
  {Dd[],D(d+1)[]}-Standard only
28{Dd[], D(d+1)[]}@8byte
  {Dd[], D(d+2)[]}@8byte
 16{Dd[], D(d+1)[]}@162-byte
  {Dd[], D(d+2)[]}@162-byte
 32{Dd[], D(d+1)[]}@324-byte
  {Dd[], D(d+2)[]}@324-byte
38, 16, or 32{Dd[], D(d+1)[], D(d+2)[]}-Standard only
  {Dd[], D(d+2)[], D(d+4)[]}-Standard only
48{Dd[], D(d+1)[], D(d+2)[], D(d+3)[]}@324-byte
  {Dd[], D(d+2)[], D(d+4)[], D(d+6)[]}@324-byte
 16{Dd[], D(d+1)[], D(d+2)[], D(d+3)[]}@648-byte
  {Dd[], D(d+2)[], D(d+4)[], D(d+6)[]}@648-byte
 32{Dd[], D(d+1)[], D(d+2)[], D(d+3)[]}@64 or @1288-byte or 16-byte
  {Dd[], D(d+2)[], D(d+4)[], D(d+6)[]}@64 or @1288-byte or 16-byte

[a] Every register in the list must be in the range D0-D31.

[b] Align can be omitted. In this case, standard alignment rules apply, see Alignment restrictions in load and store, element and structure instructions.

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