5.13.3. VMOV2

The VMOV2 pseudo-instruction generates a constant and places it in every element of a NEON vector, without loading a value from a literal pool. It always assembles to exactly two instructions.

VMOV2 can generate any 16-bit constant, and a restricted range of 32-bit and 64-bit constants.

Syntax

VMOV2{cond}.datatype Qd, #constant
VMOV2{cond}.datatype Dd, #constant

where:

datatype

must be one of:

  • I8, I16, I32, or I64

  • S8, S16, S32, or S64

  • U8, U16, U32, or U64

  • F32.

cond

is an optional condition code (see Condition codes).

Qd or Dd

is the extension register to be loaded.

constant

is a constant of the appropriate type for datatype.

Usage

VMOV2 typically assembles to a VMOV or VMVN instruction, followed by a VBIC or VORR instruction. See VMOV, VMVN (immediate) and VBIC and VORR (immediate) for details.

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