4.2.3. LDR and STR (register offset)

Load and Store with register offset, pre-indexed register offset, or post-indexed register offset.

Syntax

op{type}{cond} Rt, [Rn, +/-Rm {, shift}]   ; register offset
op{type}{cond} Rt, [Rn, +/-Rm {, shift}]!  ; pre-indexed
op{type}{cond} Rt, [Rn], +/-Rm {, shift}   ; post-indexed
opD{cond} Rt, Rt2, [Rn, +/-Rm {, shift}]   ; register offset, doubleword
opD{cond} Rt, Rt2, [Rn, +/-Rm {, shift}]!  ; pre-indexed, doubleword
opD{cond} Rt, Rt2, [Rn], +/-Rm {, shift}   ; post-indexed, doubleword

where:

op

can be either:

LDR

Load Register

STR

Store Register.

type

can be any one of:

B

unsigned Byte (Zero extend to 32 bits on loads.)

SB

signed Byte (LDR only. Sign extend to 32 bits.)

H

unsigned Halfword (Zero extend to 32 bits on loads.)

SH

signed Halfword (LDR only. Sign extend to 32 bits.)

-

omitted, for Word.

cond

is an optional condition code (see Conditional execution).

Rt

is the register to load or store.

Rn

is the register on which the memory address is based.

Rm

is a register containing a value to be used as the offset. Rm must not be r15. -Rm is not allowed in Thumb code.

shift

is an optional shift.

Rt2

is the additional register to load or store for doubleword operations.

Not all options are available in every instruction set and architecture. See Offset register and shift options for details.

Offset register and shift options

Table 4.3 shows the ranges of offsets and availability of these instructions.

Table 4.3. Options and architectures, LDR/STR (register offsets)

Instruction+/-Rm [a]shift  Arch.
ARM, word or byte [b]+/-RmLSL #0-31LSR #1-32 All
  ASR #1-32ROR #1-31RRX 
ARM, signed byte, halfword, or signed halfword+/-RmNot availableAll
ARM, doubleword+/-RmNot availablev5TE +
32-bit Thumb, word, halfword, signed halfword, byte, or signed byte [b]+RmLSL #0-3  v6T2, v7
32-bit Thumb, doubleword+RmNot availablev6T2, v7
16-bit Thumb, all except doubleword[c]+RmNot availableAll T
16-bit ThumbEE, word [b]+RmLSL #2 (required)T-2EE
16-bit ThumbEE, halfword, signed halfword [b]+RmLSL #1 (required)T-2EE
16-bit ThumbEE , byte , signed byte [b]+RmNot availableT-2EE

[a] Where +/-Rm is shown, you can use -Rm, +Rm, or Rm. Where +Rm is shown, you cannot use -Rm.

[b] For word loads, Rt can be the pc. A load to the pc causes a branch to the address loaded. In ARMv4, bits[1:0] of the address loaded must be 0b00. In ARMv5T and above, bits[1:0] must not be 0b10, and if bit[0] is 1, execution continues in Thumb state, otherwise execution continues in ARM state.

[c] Rt, Rn, and Rm must all be in the range r0-r7.


Register restrictions

In the pre-index and post-index forms:

  • Rn must be different from Rt

  • Rn must be different from Rm in architectures before ARMv6.

Doubleword register restrictions

For Thumb-2 instructions, you must not specify sp or pc for either Rt or Rt2.

For ARM instructions:

  • Rt must be an even-numbered register

  • Rt must not be lr

  • it is strongly recommended that you do not use r12 for Rt

  • Rt2 must be R(t + 1)

  • Rm must be different from Rt and Rt2 in LDRD instructions

  • Rn must be different from Rt2 in the pre-index and post-index forms.

Use of PC

In ARM instructions:

  • You can use PC for Rt in LDR word instructions and PC for Rn in LDR instructions with register offset syntax (that is the forms that do not writeback to the Rn).

  • You can use PC for Rt in STR word instructions and PC for Rn in STR instructions with register offset syntax (that is the forms that do not writeback to the Rn). However, these are deprecated.

Other uses of PC are not allowed in ARM instructions.

In Thumb instructions you can use PC for Rt in LDR word instructions. Other uses of PC in these Thumb instructions are not allowed.

Use of SP

You can use SP for Rn.

In ARM, you can use SP for Rt in word instructions. Uses of SP for Rt in non-word instructions are deprecated in ARM code.

In Thumb, you can use SP for Rt in word instructions only. All other use of SP for Rt in these instructions are unpredictable in Thumb code.

Use of SP for Rm is unpredictable in Thumb state and deprecated in ARM state.

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