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| Home > NEON and VFP Programming > NEON load / store element and structure instructions > Alignment restrictions in load and store, element and structure instructions | |||
Many of these instructions allow memory alignment restrictions to be specified. When the alignment is not specified in the instruction, the alignment restriction is controlled by the A bit (CP15 register 1 bit[1]):
if the A bit is 0, there are no alignment restrictions (except for strongly ordered or device memory, where accesses must be element aligned or the result is unpredictable)
if the A bit is 1, accesses must be element aligned.
If an address is not correctly aligned, an alignment fault occurs.
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