5.12.2. Alignment restrictions in load and store, element and structure instructions

Many of these instructions allow memory alignment restrictions to be specified. When the alignment is not specified in the instruction, the alignment restriction is controlled by the A bit (CP15 register 1 bit[1]):

If an address is not correctly aligned, an alignment fault occurs.

Copyright © 2002-2010 ARM. All rights reserved.ARM DUI 0204J