4.10.9. DBG, DMB, DSB, and ISB

Debug, Data Memory Barrier, Data Synchronization Barrier, and Instruction Synchronization Barrier.

Syntax

DBG{cond} {#option}
DMB{cond} {#option}
DSB{cond} {#option}
ISB{cond} {#option}

where:

cond

is an optional condition code (see Conditional execution).

option

is an optional limitation on the operation of the hint.

Usage

These are hint instructions. It is optional whether they are implemented or not. If any one of them is not implemented, it behaves as a NOP.

DBG

Debug hint provides a hint to debug and related systems. See their documentation for what use (if any) they make of this instruction.

DMB

Data Memory Barrier acts as a memory barrier. It ensures that all explicit memory accesses that appear in program order before the DMB instruction are observed before any explicit memory accesses that appear in program order after the DMB instruction. It does not affect the ordering of any other instructions executing on the processor.

Allowed values of option are:

SY

Full system DMB operation. This is the default and can be omitted.

ST

DMB operation that waits only for stores to complete.

ISH

DMB operation only to the inner shareable domain.

ISHST

DMB operation that waits only for stores to complete, and only to the inner shareable domain.

NSH

DMB operation only out to the point of unification.

NSHST

DMB operation that waits only for stores to complete and only out to the point of unification.

OSH

DMB operation only to the outer shareable domain.

OSHST

DMB operation that waits only for stores to complete, and only to the outer shareable domain.

DSB

Data Synchronization Barrier acts as a special kind of memory barrier. No instruction in program order after this instruction executes until this instruction completes. This instruction completes when:

  • All explicit memory accesses before this instruction complete.

  • All Cache, Branch predictor and TLB maintenance operations before this instruction complete.

Allowed values of option are:

SY

Full system DSB operation. This is the default and can be omitted.

ST

DSB operation that waits only for stores to complete.

ISH

DSB operation only to the inner shareable domain.

ISHST

DSB operation that waits only for stores to complete, and only to the inner shareable domain.

NSH

DSB operation only out to the point of unification.

NSHST

DSB operation that waits only for stores to complete and only out to the point of unification.

OSH

DSB operation only to the outer shareable domain.

OSHST

DSB operation that waits only for stores to complete, and only to the outer shareable domain.

ISB

Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. It ensures that the effects of context altering operations, such as changing the ASID, or completed TLB maintenance operations, or branch predictor maintenance operations, as well as all changes to the CP15 registers, executed before the ISB instruction are visible to the instructions fetched after the ISB.

In addition, the ISB instruction ensures that any branches that appear in program order after it are always written into the branch prediction logic with the context that is visible after the ISB instruction. This is required to ensure correct execution of the instruction stream.

Allowed values of option are:

SY

Full system ISB operation. This is the default, and can be omitted.

Alias

The following alternative values of option are supported for DMB and DSB, but ARM recommends that you do not use them:

  • SH is an alias for ISH

  • SHST is an alias for ISHST

  • UN is an alias for NSH

  • UNST is an alias for NSHST

Architectures

These ARM and 32-bit Thumb instructions are available in ARMv7.

There are no 16-bit Thumb versions of these instructions.

Copyright © 2002-2010 ARM. All rights reserved.ARM DUI 0204J
Non-ConfidentialID101213