4.3.13. SDIV and UDIV

Signed and Unsigned Divide.

Syntax

SDIV{cond} {Rd}, Rn, Rm
UDIV{cond} {Rd}, Rn, Rm

where:

cond

is an optional condition code (see Conditional execution).

Rd

is the destination register.

Rn

is the register holding the value to be divided.

Rm

is a register holding the divisor.

Register restrictions

pc or sp cannot be used for Rd, Rn or Rm.

Architectures

These 32-bit Thumb instructions are available in ARMv7-R and ARMv7-M only.

There are no ARM or 16-bit Thumb SDIV and UDIV instructions.

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