5.13.2. VLDR and VSTR (post-increment and pre-decrement)

Pseudo-instructions that load or store extension registers with post-increment and pre-decrement.

Note

See VLDR and VSTR for information on the VLDR and VSTR instructions without post-increment and pre-decrement.

Syntax

op{cond}{.size} Fd, [Rn], #offset          ; post-increment
op{cond}{.size} Fd, [Rn, #-offset]!        ; pre-decrement

where:

op

can be:

  • VLDR - load extension register from memory

  • VSTR - store contents of extension register to memory.

cond

is an optional condition code (see Condition codes).

size

is an optional data size specifier. Must be 32 if Fd is a single precision VFP register, or 64 if Fd is a double precision register.

Fd

is the extension register to be loaded or saved. For a NEON instruction, it must be a double precision (Dd) register. For a VFP instruction, it can be either a double precision (Dd) or a single precision (Sd) register.

Rn

is the ARM register holding the base address for the transfer.

offset

is a numeric expression that must evaluate to a numeric constant at assembly time. The value must be 4 if Fd is a single precision VFP register, or 8 if Fd is a double precision register.

Usage

The post-increment instruction increments the base address in the register by the offset value, after the transfer. The pre-decrement instruction decrements the base address in the register by the offset value, and then performs the transfer using the new address in the register. These pseudo-instructions assemble to VLDM or VSTM instructions (see VLDM, VSTM, VPOP, and VPUSH).

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