5.1.2. Shared NEON and VFP instructions

Table 5.2 shows a summary of instructions that are common to NEON and VFP.

Table 5.2. Location of shared NEON and VFP instructions

MnemonicBrief descriptionPageOp.Arch.
VLDMLoad multipleVLDM, VSTM, VPOP, and VPUSH-All
VLDRLoad (see also VLDR pseudo‑instruction)VLDR and VSTRScalarAll
 Load (post-increment and pre-decrement)VLDR and VSTR (post-increment and pre-decrement)ScalarAll
VMOVTransfer from one ARM® register to half of a doubleword registerVMOV (between an ARM register and a NEON scalar)ScalarAll
 Transfer from two ARM registers to a doubleword registerVMOV (between two ARM registers and an extension register)ScalarVFPv2
 Transfer from half of a doubleword register to ARM registerVMOV (between an ARM register and a NEON scalar)ScalarAll
 Transfer from a doubleword register to two ARM registersVMOV (between two ARM registers and an extension register)ScalarVFPv2
 Transfer from single-precision to ARM registerVMOV (between one ARM register and single precision VFP)ScalarAll
 Transfer from ARM register to single-precisionVMOV (between one ARM register and single precision VFP)ScalarAll
VMRSTransfer from NEON and VFP system register to ARM registerVMRS and VMSR-All
VMSRTransfer from ARM register to NEON and VFP system registerVMRS and VMSR-All
VPOPPop VFP or NEON registers from full-descending stackVLDM, VSTM, VPOP, and VPUSH-All
VPUSHPush VFP or NEON registers to full-descending stackVLDM, VSTM, VPOP, and VPUSH-All
VSTMStore multipleVLDM, VSTM, VPOP, and VPUSH-All
VSTRStoreVLDR and VSTRScalarAll
 Store (post-increment and pre-decrement)VLDR and VSTR (post-increment and pre-decrement)ScalarAll

Copyright © 2002-2010 ARM. All rights reserved.ARM DUI 0204J
Non-ConfidentialID101213